Shift Register: different behaviour between QII 8.0 and 10.1

[Altera_Forum]

I have created the following shift register using Quartus II 8.0: 

 entity shiftreg is generic ( data_size : integer := 8 ); port ( clk : in std_logic; clr : in std_logic; data_in : in std_logic; data_out : out std_logic_vector (data_size - 1 downto 0) ); end shiftreg;   architecture shiftreg of shiftreg is signal data_wire : std_logic_vector (data_size - 1 downto 0);   begin process (clk, clr, data_in, data_wire)   variable count_data : integer;   begin   if (clr = '1') then data_wire <= (others =>'0'); else if (clk'event and clk = '1') then data_wire(data_size - 1 downto 1) <= data_wire(data_size - 2 downto 0); data_wire(0) <= data_in; end if; end if;   end process;   data_out <= data_wire; end shiftreg;  Performed the simulation using Altera-ModelSIM 6.6c and obtained the "correct" results as shown in Fig. 1.   After creating a new project and compile it using Quartus II 10.1, I have performed a new simulation (same stimuli) and obtained the "incorrect" behaviour as shown in Fig. 2.   Used Timequest to guide the placement and verified with the Technology Map Viewer (post-fiiting) that the resource usage and netlist are indeed the same in both version of Quartus (clearly the device used was also consistent EP1C12Q240C7).   Is this a problem related with the simuation tool and its libraries? what is that I am missing?   Thanks in advance for any reply

[Altera_Forum]

Is your design properly constrained in Timequest and does it meet all timing requirements?

[Altera_Forum]

The design is constrained correctly for Input, Output and for clock. As mentioned, the interesting aspect is that the Technology Map Viewer shows the same implementation, thus, the propagation delays should also be consistent between the 2 designs. 

 I am planning to submit a Request and send the archive project to Altera: would be the project of interest to You?

[Altera_Forum]

The timing models for Modelsim could be different between the two versions and it could explain the different results even with the same synthesis. Also please note that even if the technology map viewer shows the same implementation, the two versions of Quartus could route the design differently, giving slightly different delays. But if the design is properly constrain and you don't have any critical warning from Timequest then this shouldn't happen and you should have consistent results in the two cases. 

This could sound stupid but are you sure that the clock you use in your testbench is within the range you specified in the timing constraints?

[Altera_Forum]

Indeed, the clock is also constrained and I am not getting any error or warning from Timequest. 

I have double checked for unconstrained paths and everything looks OK.  An interesting aspect is that I have also created a new design under 101. in which I am using an Enable Shift signal and, surprise surprise, it works fine. The only doubt that I would like to dissipate is to verify that, in fact, the first design was created under Quartus II 8.0 and that project has been then opened with Quartus II 10.1. I will further test if this could be a condition for the reported problem by creating a brand new project (different directories but same design file) under Quartus 8.0 and then open it under 10.1. While it could be a glitch of either tool, I am a bit concern about this misbehaviour because I have quite some projects created with 8.0 that will end up in 10.1 or later versions. I will keep posting any result.

[Altera_Forum]

So, I have been trying further and I came to the conlcusion that the problem has been generated not between QII 8.0 and 10.1 but between QII 10.1 and 10.1 SP1. 

Indeed, the original design, for which I have posted the VHDL code, was created with a project under 10.1. I have then upgraded to SP1 and once I have opened the project I have been asked to update the database, which I did, and that is when I have seen the strange behavior of ModelSIM. In the past day, I have create a new project with the same code under 10.1 SP1 and same code and it behaved correctly. I do not know if it is the case to submit a service request considering that this version of QII has been already superseded by the latters: at least I know, or at I believe to understand, the failure mechanism.   Thanks for the support,    Armando

[Altera_Forum]

It indeed looks like a bug. If you can check that this is still a problem with Quartus II 11.1 SP2 then you can file an SR, but if not then I don't think it's worth the while, I don't think they would fix it if it only impacted 10.1 SP1