Shortening NIOSII Simulation run time with FPGA SOC system as recommended in AN351

[AAnch]

Hi, As described below i have simulated with NIOSII, RAM & JTAG UART qsys system. Compiled and simulated the example Hello World C code program. From the simulation i see that it takes around 2 ms to complete the simulation. Before the NIOSII starts executing the main code to start printing the message on the JTAG UART port (NIOS instruction port to JTAG UART trasfers), there are a lot of NIOSII data port bus to SRAM accesses. Is it possible to shorten the boot code execution and instead do memory initialisation for FPGA simulation purposes?

[GuaBin_N_Intel]

There is not much setting you can set to reduce the simulation time. Try to enable this "enable_sim_optimize" in bsp setting "https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/nios2/n2sw_nii5v2gen2.pdf, pg465

[AAnch]

Hello,

Well, I am not really looking for any compiler options to shorten the simulation time. But when I see in model sim simulations, during the boot code execution before jumping to main there is lot of operations performed by the NIOSII data bus on the internal onchip RAM. So my request is: Is there a possibility to remove some operations from the boot code and replace them with initialising the onchip RAM components (Note this is only for simulation purposes). Initialising the memory instead of doing writes to memory will directly shorten the boot code execution simulation time. I understand on the FPGA it will be the actual boot code that runs.

Thanks,

Arvind

[GuaBin_N_Intel]

​No, it is not possible to do code initialization. The simulation flow must follow how NIOS operates in actual way.