Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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16496 Discussions

SignalTap JTAG Configuration Error/Invalid


I'm trying to verify/debug a program on a Cyclone IV E: EP4CE40F23I7. When I try to use the Signal Tap Logic Analyzer, the JTAG Chain Configuration status says JTAG ready, but the Instance Manager says Invalid JTAG configuration. When I try to Run Analysis, the instance status changes to instance not found. And whilst, the board is successfully programmed via JTAG (verified on oscilloscope and blinky LED). What can possibly be causing this Signal Tap analysis function with JTAG?

I've generated the .sof via compilation, and I've created the .stp in the Signal Tap Logic Analyzer wizard. The .stp has been enabled for the project in the Assignments > Settings window. The design has been successfully compiled, and the files sld_hub:auto_hub and sld_signaltap:sigtap_inst_001 have been generated and placed in the hierarchy. I've attached the .sof file and verified with the SOF manager. When I press the Program Device button, the chain config status shows Programming Device, while the instance manager says Waiting for JTAG, then they change back to JTAG ready and Invalid JTAG configuration, respectively. 

I've watched the Intel-provided Signal Tap training course, and it suggests that the only thing necessary to make the instance is to make the .stp, enable it in the settings window, compile, then program. I've done that. Some boards have also suggested timing constraints on altera_reserved_tck (tried it already), unplug/plug USB (done it), cycle power to board and/or PC (done both), only have one instance of Quartus open (done that). I don't know what else to try/where else to look. What else is there that can be done without administration privileges? The last thing I will try is uninstall and reinstall Quartus.

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I observed that you have 2 SignalTap instances in your stp file. Is both the stp file included into your design? Could you share with me your Quartus design and Quartus report file (.rpt)?

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