SignalTap seems to not show all internal signals within my module. I have to sometimes write an output port in order to view them. Is there a way to force showing internal signals that are there but not showing up when trying to add nodes?
I tried both post-fitting and pre-synthesis filters and ensured I looked in the correct "Look in" location (both in toplevel and the specific module).链接已复制
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Thanks ted for the reply!!
Wow, didn't think it was that simple. I guess the compiler removes the nodes that are redundant during its optimization process. Keep: --- Quote Start --- You cannot use this synthesis attribute for nodes that have no fan-out. To use the keep synthesis attribute, you can specify the keep synthesis attribute in a comment that is on the same line as the combinational node you want Analysis & Synthesis to keep. In the comment, precede the synthesis attribute with the synthesis keyword. For example, in the following code, the comment /* synthesis keep */ directs Analysis & Synthesis to not minimize the keep_wire combinational node: wire keep_wire /* synthesis keep */; --- Quote End --- Preserve: --- Quote Start --- There are two important limitations of the preserve synthesis attribute: It prevents a register from being inferred as a state machine. It does not preserve fanout-free registers. Use the noprune synthesis attribute to prevent Analysis & Synthesis from removing fanout-free registers. You can use Verilog 2001 attribute syntax to preserve a register, as shown in the following code: (*preserve*) reg reg1; You can also embed the attribute in a block comment that follows the variable declaration for the register you wish to preserve. You can also set the attribute on a module, which directs Analysis & Synthesis to preserve all registers in the module, except for those registers that infer state machines. For example, in the following code, the comment /* synthesis preserve */ directs Analysis & Synthesis to preserve the reg1 register: reg reg1 /* synthesis preserve */; --- Quote End ---