Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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16021 Discussions

SignalTap does not show trigger pulse at the same sample number everytime

New Contributor II

In SignalTap II it is possible to specify the trigger position as e.g as centre trigger position. When trigger condition is met, the sample number where the condition was met will always be at the same location e.g center of the display for center trigger position.

If we have selected 128 sample depth, the trigger condition will be around sample 64 *consistently*! The sample number where trigger condition is met will always appear on the same location every time SignalTap II triggers and shows the result.

In the past I have observed many times that when using segmented SignalTap II instance, we have a situation where for a given system, certain combinations of sample depth and segment count, the trigger point shows a jitter. This means that when data appears on SignalTap II after trigger condition being met, the trigger point sample number will be a few samples before or after the correct sample number. This only happens when segmented buffer is used! I have not been able to predict when this bug should happen so far. Using trial and error or by using a different combination of sample depth and segment count, it is possible to cause the problem to go away. The issue here is that since Quartus projects take such a long time to compile, it ends up wasting a huge amount of time trying to recompile project just to get SignalTap II to work consistently.

Why does signal tap have this bug? I am sure many other people have observed it as well at some point during their usage.

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7 Replies
Honored Contributor III

I have never seen this.  I think you'd have to show an example of what's happening.  Remember that with a segmented buffer, you have to think of each segment like a full buffer, so the trigger position should be the same in each segment.  Depending on the trigger conditions or if you've enabled storage qualification, the trigger position may not be at the same location.


May I know does the sstrell's suggestion help in anyway for your case? Do you need further help on this? 

New Contributor II

I cannot share the full design now. I shall see if/when it occurs in a dummy design, I shall share it here.

Honored Contributor III

You could just post Signal Tap screenshots, including the Data and Setup tabs.  You don't really need to post the design itself.


Any update from your side? 

New Contributor II

Please close this item for now as I cannot provide an image to you at this time.


Thanks for your confirmation to close this case. I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,
Richard Tan

p/s: If any replies from the Intel or community support are helpful, please feel free to give Kudos.