I'm the student and the beginner at FPGA. I found some people who had the same problem. I think I checked what they did, but the problem still exists. Please help me. I uploaded one minute video. Sorry for bad English because I'm Korean student. But you can see the window and it may help you to find the problem. I also uploaded the file.
I really hope you to help me.
The module in your HDL is named "hello" which doesn't match what you've specified as the top-level entity ("2_2_Hello_Word"). Either change the HDL code or the name of the top-level entity in the project settings.
Also note that none of that HDL code in 2_2_Hello_Word.v is synthesizable so compiling it in Quartus isn't going to do anything. The code you've written is more like what would be a simulation testbench for a simulation tool like ModelSim.
I really appreciate your help. After I changed my module name, the different error which you said occurred.
"Error (12061): Can't synthesize current design -- Top partition does not contain any logic"
The code was from the first part of the book and I think I really have to change the book to study,,,
Since you are starting to design FPGA, you may checkout the course below as a starting point.
After that, you may checkout the webpage below to further explore courses that you are interested to learn. (fyi: How to Begin a Simple FPGA Design course is under FPGA Designers - level 200)
Hope it helps in your FPGA journey.
I believed that your question has been addressed, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
p/s: If any replies from the Intel or community support are helpful, please feel free to give Kudos.