Signals in Testbench

[Altera_Forum]

Hi, 

 This might be very easy question but I'm new to FPGA.  I have a signal which is called "tx_busy_s" with an initial value '0'. But this signal comes as "U" in the simulation.   I use Test bench Template Writer, but in the test bench it doesn't recognize my signal because it's not in my entity. So I tried to define it as a signal in the test bench, but this time it comes as a new signal in the simulation, not as the signal in the main code.  How can I give an initial value to my signal in the test bench? And why does the other signal "tx_start_s" come with an initial value '0' in the simulation? I mean, what's the difference between those two?  This is my main code: library IEEE;use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; ------------------------------------------------------------------------------- Entity mixuart is PORT ( Clock_50: in std_logic; Sw: in std_logic_vector(9 downto 0); Key: in std_logic_vector(3 downto 0); ledg: out std_logic_vector(7 downto 0); uart_txd: out std_logic ); End mixuart; ------------------------------------------------------------------------------- Architecture mixuart_a of mixuart is ------------------------------------------------------------------------------- signal tx_data_s: std_logic_vector(7 downto 0); signal tx_start_s: std_logic:='0'; signal tx_busy_s: std_logic:='0'; ------------------------------------------------------------------------------- Component Tx PORT( Clk: in std_logic; Start: in std_logic; Busy: out std_logic; Data: in std_logic_vector(7 downto 0); Tx_line: out std_logic ); End Component Tx; ------------------------------------------------------------------------------- BEGIN C1: Tx PORT MAP (Clock_50, Tx_start_s, Tx_busy_s, Tx_data_s, uart_txd); ------------------------------------------------------------------------------- PROCESS(Clock_50) BEGIN IF(Clock_50'event and clock_50='1') then IF(Key(0)='0' and Tx_busy_s='0') then Tx_data_s<=Sw(7 downto 0); Tx_start_s<='1'; Ledg<=Tx_data_s; ELSE Tx_start_s<='0'; END IF; END IF; END PROCESS; ------------------------------------------------------------------------------- END mixuart_a;   Thank you.

[Altera_Forum]

According to your code, tx_busy_s should be '0' and stay '0'. Are you sure the waveform you're looking at is for the code you posted?

[Altera_Forum]

Yes, I am. I took a screenshot and highlighted two signals. One of them comes from the test bench as I mentioned before. So you can see, if I don't force the signal "/mixuart2_vhd_tst/i1/tx_busy_s" to be '0', it doesn't work.  

 And also, why does tx_busy_s stay '0'? I'm expecting it to be '1' when "Start" goes '1'.   Here is a picture of the simulation:  https://www.alteraforum.com/forum/attachment.php?attachmentid=8213   Main Code:  library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; ------------------------------------------------------------------------------- Entity mixuart2 is PORT ( Clock_50: in std_logic; Sw: in std_logic_vector(7 downto 0); Key: in std_logic; Reset: in std_logic; ledg: out std_logic_vector(7 downto 0); uart_txd: out std_logic ); End mixuart2; ------------------------------------------------------------------------------- Architecture mixuart_a of mixuart2 is ------------------------------------------------------------------------------- signal tx_data_s: std_logic_vector(7 downto 0); signal tx_start_s: std_logic:='0'; signal tx_busy_s: std_logic:='0'; ------------------------------------------------------------------------------- Component Tx PORT( Clk: in std_logic; Start: in std_logic; Busy: out std_logic; Data: in std_logic_vector(7 downto 0); Tx_line: out std_logic; Stop: in std_logic ); End Component Tx; ------------------------------------------------------------------------------- BEGIN C1: Tx PORT MAP (Clock_50, Tx_start_s, Tx_busy_s, Tx_data_s, uart_txd,Reset); ------------------------------------------------------------------------------- PROCESS(Clock_50,Reset) BEGIN IF (Clock_50'event and Clock_50='1') then IF (Reset='1') then Tx_start_s<='0'; ELSIF(Key='1' and Tx_busy_s='0') then Tx_data_s<=Sw; Tx_start_s<='1'; Ledg<=Tx_data_s; ELSE Tx_start_s<='0'; END IF; END IF; END PROCESS; ------------------------------------------------------------------------------- END mixuart_a;   Tx: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------- Entity Tx is PORT( Clk: in std_logic; Start: in std_logic; busy: out std_logic; data: in std_logic_vector(7 downto 0); tx_line: out std_logic; Stop: in std_logic ); End Tx; ------------------------------------------------------------------------------- Architecture tx_a of tx is ------------------------------------------------------------------------------- signal clk_div_s: integer range 0 to 5208:=0; signal index_s: integer range 0 to 9:=0; signal datafll_s: std_logic_vector(9 downto 0); signal tx_flag_s: std_logic:='0'; ------------------------------------------------------------------------------- BEGIN PROCESS(Clk,Stop) BEGIN IF(Clk'event and clk='1') THEN IF (Stop='1') THEN tx_flag_s<='0'; busy<='0'; datafll_s(8 downto 1)<="00000000"; index_s<=0; clk_div_s<=0; ELSIF(tx_flag_s='0' and Start='1') THEN tx_flag_s<='1'; busy<='1'; datafll_s(0)<='0'; datafll_s(9)<='1'; datafll_s(8 downto 1)<=data; END IF; IF(tx_flag_s='1') THEN IF(clk_div_s<5207) THEN clk_div_s<=clk_div_s+1; ELSE clk_div_s<=0; END IF; IF(clk_div_s=2600)THEN Tx_line<=datafll_s(index_s); IF(index_s<9) THEN index_s<=index_s+1; ELSE tx_flag_s<='0'; busy<='0'; index_s<=0; END IF; END IF; END IF; END IF; ------------------------------------------------------------------------------- END PROCESS; END tx_a;   Test bench: LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mixuart2_vhd_tst IS END mixuart2_vhd_tst; ARCHITECTURE mixuart2_arch OF mixuart2_vhd_tst IS -- constants -- signals SIGNAL Clock_50 : STD_LOGIC; SIGNAL Key : STD_LOGIC; SIGNAL ledg : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL Reset : STD_LOGIC; SIGNAL Sw : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL uart_txd : STD_LOGIC; signal tx_busy_s : Std_LOGIC; constant clk_period: time:=20ns; COMPONENT mixuart2 PORT ( Clock_50 : IN STD_LOGIC; Key : IN STD_LOGIC; ledg : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); Reset : IN STD_LOGIC; Sw : IN STD_LOGIC_VECTOR(7 DOWNTO 0); uart_txd : OUT STD_LOGIC ); END COMPONENT; BEGIN i1 : mixuart2 PORT MAP ( -- list connections between master ports and signals Clock_50 => Clock_50, Key => Key, ledg => ledg, Reset => Reset, Sw => Sw, uart_txd => uart_txd ); init : PROCESS -- variable declarations BEGIN Clock_50<='0'; wait for clk_period/2; Clock_50<='1'; wait for clk_period/2; END PROCESS init; always : PROCESS -- optional sensitivity list -- ( ) -- variable declarations BEGIN tx_busy_s<='0'; Reset<='0'; Key<='0'; Sw<="00110011"; wait for 50 ns; key<='1'; wait for 10 us; WAIT; END PROCESS always; END mixuart2_arch;   Thank you.

[Altera_Forum]

The tx_busy_s in your testbench in set to '0' in the "always" process and never set to anything else (thats the first highlighted signal) 

 The other highlight takes the busy signal from inside the Tx block, which isnt assigned a reset value (therefore uninitialised) and stop, start and tx_flag_s arnt at a condition to set busy to any values yet. Hence the 'U' value.

[Altera_Forum]

Thank you for your help. I've made some changes according to your explanation and it works.