Simulating 2 different devices in a single testbench

[shaiko]

Hello,

My system involves 2 FPGAs communication over a Serial Lite III interface in duplex configuration.

The devices are as follows:
1. Arria 10 - project is implemented using Quartus 23.2
2. Stratix 10 - project is implemented using Quartus 23.1

I was able to successfully simulate each top hierarchy in its separate testbench using Questa.
Now, I want to instantiate the 2 top hierarchies under a single unified testbench.

Is this possible ?
How can I handle the separate msim_setup.tcl scripts generated using 2 different Quartus versions ?

[ShengN_Intel]

Hi,

Can instantiate the 2 top hierarchies under a single unified testbench but may have to comment out either one Arria 10 or Stratix 10 instantiation as can't simulate both at the same time. Because that's not possible to handle separate msim_setup.tcl scripts at the same time. Separate msim_setup.tcl scripts will have different simulation environment variables. When sourcing different msim_setup.tcl scripts, the simulation environment variables will be overridden and eventually will cause some path unfound problem.

Thanks,

Regards,

Sheng

[shaiko]

---

@ShengN_Intel wrote:

Can instantiate the 2 top hierarchies under a single unified testbench but may have to comment out either one Arria 10 or Stratix

---

The purpose of having them BOTH under the same testbench is to be able to simulate them communicating with each other.

Is it possible to somehow modify the msim_setup.tcl scripts to make it work ?

[ShengN_Intel]

Hi,

I had done trying and found out the following steps (have to manually modify and merge the simulation tcl scripts):

1.Create a new folder duplicate of for example Arria 10 project.

2.In newly created Arria 10 project GUI, copy and include the Stratix 10 project design files, .qsys and .ip related files and folders.

3.Perform ip upgradation, full compilation and go to Tools -> Generate Simulator Setup Script for IP (combined)

4.Again in newly created Arria 10 project, copy the old Stratix 10 project .qsys, .ip related files and folders to replace the previously copied, upgraded Stratix 10 project .qsys and .ip related files/folders. This time don't perform ip upgradation.

5.Between the newly created Arria 10 project and old Stratix 10 project, compare, modify and merge the files mentor/msim_setup.tcl, common/modelsim_files.tcl and common/ncsim_files.tcl

6.Lastly, source necessary's files in simulation script file and run simulation.

Thanks,

Best Regards,

Sheng

[shaiko]

I tried your proposed solution and it fails in step #3.

After adding the Stratix files into the Arria project I ran the IP upgrade tool and it fails.

Error: 2023.10.31.20:54:09 Error: The system and spd files are targeted to multiple device families "arria10,stratix10". Please regenerate your designs using same device family. If your designs are family-independent, use --device-family to specify one device family.
Error(20327): 2023.10.31.20:48:50 Error: reset_release_stratix: Component s10_user_rst_clkgate_0 does not support selected device family Arria 10
Error(20327): 2023.10.31.20:48:50 Error: Generation failed with exit code 3: 1 Error, 0 Warnings
Error(20327): 2023.10.31.20:48:50 Error: Device part 1SG280HU2F50E2VG is not a valid part in the device family Arria 10
Error(20327): 2023.10.31.20:48:50 Error: reset_release_stratix: Component s10_user_rst_clkgate_0 does not support selected device family Arria 10
Error(20327): 2023.10.31.20:48:50 Error: Generation failed with exit code 3: 1 Error, 0 Warnings
Error(20327): 2023.10.31.20:49:07 Error: pll_atx_stratix.xcvr_atx_pll_s10_htile_0: The current selected device "10AX115S2F45I1SG" is invalid, please select a valid device to generate the IP.
Error(20327): 2023.10.31.20:49:07 Error: pll_atx_stratix: Component xcvr_atx_pll_s10_htile_0 does not support selected device family Arria 10
Error(20327): 2023.10.31.20:49:07 Error: Generation failed with exit code 3: 2 Errors, 0 Warnings
Error(20327): 2023.10.31.20:49:07 Error: Device part 1SG280HU2F50E2VG is not a valid part in the device family Arria 10
Error(20327): 2023.10.31.20:49:07 Error: pll_atx_stratix.xcvr_atx_pll_s10_htile_0: The current selected device "10AX115S2F45I1SG" is invalid, please select a valid device to generate the IP.
Error(20327): 2023.10.31.20:49:07 Error: pll_atx_stratix: Component xcvr_atx_pll_s10_htile_0 does not support selected device family Arria 10
Error(20327): 2023.10.31.20:49:07 Error: Generation failed with exit code 3: 2 Errors, 0 Warnings
Error(20327): 2023.10.31.20:49:15 Error: fpll_user_stratix.xcvr_fpll_s10_htile_0: The current selected device "10AX115S2F45I1SG" is invalid, please select a valid device to generate the IP.
Error(20327): 2023.10.31.20:49:15 Error: fpll_user_stratix: Component xcvr_fpll_s10_htile_0 does not support selected device family Arria 10
Error(20327): 2023.10.31.20:49:15 Error: Generation failed with exit code 3: 2 Errors, 1 Warning
Error(20327): 2023.10.31.20:49:15 Error: Device part 1SG280HU2F50E2VG is not a valid part in the device family Arria 10
Error(20327): 2023.10.31.20:49:15 Error: fpll_user_stratix.xcvr_fpll_s10_htile_0: The current selected device "10AX115S2F45I1SG" is invalid, please select a valid device to generate the IP.
Error(20327): 2023.10.31.20:49:15 Error: fpll_user_stratix: Component xcvr_fpll_s10_htile_0 does not support selected device family Arria 10
Error(20327): 2023.10.31.20:49:15 Error: Generation failed with exit code 3: 2 Errors, 1 Warning
Error(20327): 2023.10.31.20:49:47 Error: serial_lite_iii_stratix.sl3_0: Please select a device that supports a minimum of one of the tiles, L-Tile or H-Tile.
Error(20327): 2023.10.31.20:49:47 Error: serial_lite_iii_stratix.sl3_0: add_connection: There is no interface inst_interlaken_phy.reconfig_clk
Error(20327): 2023.10.31.20:49:48 Error: serial_lite_iii_stratix.sl3_0.inst_sl3_phy.inst_phy_adapter.txcore_clock: inst_phy_adapter.txcore_clock must be connected to a clock output
Error(20327): 2023.10.31.20:49:48 Error: serial_lite_iii_stratix.sl3_0.inst_sl3_phy.inst_phy_adapter.rxcore_clock: inst_phy_adapter.rxcore_clock must be connected to a clock output
Error(20327): 2023.10.31.20:49:48 Error: serial_lite_iii_stratix.sl3_0.inst_sl3_phy: Interface tx_serial_data tried to export unknown interface inst_interlaken_phy.tx_serial_data
Error(20327): 2023.10.31.20:49:48 Error: serial_lite_iii_stratix.sl3_0.inst_sl3_phy: Interface rx_serial_data tried to export unknown interface inst_interlaken_phy.rx_serial_data
Error(20327): 2023.10.31.20:49:48 Error: serial_lite_iii_stratix.sl3_0: Interface tx_serial_data tried to export unknown interface inst_sl3_phy.tx_serial_data
Error(20327): 2023.10.31.20:49:48 Error: serial_lite_iii_stratix.sl3_0: Interface rx_serial_data tried to export unknown interface inst_sl3_phy.rx_serial_data
Error(20327): 2023.10.31.20:49:48 Error: serial_lite_iii_stratix: Component sl3_0 does not support selected device family Arria 10
Error(20327): 2023.10.31.20:49:48 Error: Generation failed with exit code 3: 9 Errors, 35 Warnings
Error(20327): 2023.10.31.20:49:48 Error: Device part 1SG280HU2F50E2VG is not a valid part in the device family Arria 10
Error(20327): 2023.10.31.20:49:48 Error: serial_lite_iii_stratix.sl3_0: Please select a device that supports a minimum of one of the tiles, L-Tile or H-Tile.
Error(20327): 2023.10.31.20:49:48 Error: serial_lite_iii_stratix.sl3_0: add_connection: There is no interface inst_interlaken_phy.reconfig_clk
Error(20327): 2023.10.31.20:49:48 Error: serial_lite_iii_stratix.sl3_0.inst_sl3_phy.inst_phy_adapter.txcore_clock: inst_phy_adapter.txcore_clock must be connected to a clock output
Error(20327): 2023.10.31.20:49:48 Error: serial_lite_iii_stratix.sl3_0.inst_sl3_phy.inst_phy_adapter.rxcore_clock: inst_phy_adapter.rxcore_clock must be connected to a clock output
Error(20327): 2023.10.31.20:49:48 Error: serial_lite_iii_stratix.sl3_0.inst_sl3_phy: Interface tx_serial_data tried to export unknown interface inst_interlaken_phy.tx_serial_data
Error(20327): 2023.10.31.20:49:48 Error: serial_lite_iii_stratix.sl3_0.inst_sl3_phy: Interface rx_serial_data tried to export unknown interface inst_interlaken_phy.rx_serial_data
Error(20327): 2023.10.31.20:49:48 Error: serial_lite_iii_stratix.sl3_0: Interface tx_serial_data tried to export unknown interface inst_sl3_phy.tx_serial_data
Error(20327): 2023.10.31.20:49:48 Error: serial_lite_iii_stratix.sl3_0: Interface rx_serial_data tried to export unknown interface inst_sl3_phy.rx_serial_data
Error(20327): 2023.10.31.20:49:48 Error: serial_lite_iii_stratix: Component sl3_0 does not support selected device family Arria 10
Error(20327): 2023.10.31.20:49:48 Error: Generation failed with exit code 3: 9 Errors, 35 Warnings
Error(14923): Error upgrading Platform Designer file "User/IP/serial_lite_iii_stratix/serial_lite_iii_stratix.ip"
Error(11133): IP component altera_sl3 with file "User/IP/serial_lite_iii_stratix/serial_lite_iii_stratix.ip" upgrade failed
Error(23031): Evaluation of Tcl script c:/intelfpga_pro/23.2/quartus/common/tcl/internal/ip_regen/ip_regen.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 43 errors, 72 warnings
Error: Peak virtual memory: 453 megabytes
Error: Processing ended: Tue Oct 31 20:49:51 2023
Error: Elapsed time: 00:11:19
Error: System process ID: 27696
Error: Peak virtual memory: 453 megabytes
Error: Processing ended: Tue Oct 31 20:49:51 2023
Error: Elapsed time: 00:11:19
Error: System process ID: 27696

[ShengN_Intel · Accepted solution]

Hi,

Seems like some IPs are only available for Stratix 10. If that's the case you may skip steps 3 and 4, straight away go to step 5 manually compare, modify and merge the files mentor/msim_setup.tcl, common/modelsim_files.tcl and common/ncsim_files.tcl between Arria 10 project and Stratix 10 project.

Thanks,

Regards,

Sheng