Reset Release IP VHDL code not working

[MATRIX7878]

Hello,

     I am trying to create a simple VHDL design test for an Agilex 7 m-series FPGA and have hit a snag.  I am trying to create a Reset Release IP code snippet and cannot seem to figure out what to do.  I do not know what is declared in the IP itself and tried working with the code I saw on the RRIP video.  I am attaching my code and the errors I am getting.  Any help would be appreciated.

Thank you,

Drew

[FvM]

Hi,
the message tells about VHDL syntax errors, a bit different from "not working".

It's generally a good idea to fix syntax errors from top to bottom, succeeding erors may be just aftereffects.

First errors are incorrect component declarations. 
Component declarations follows this scheme

component_declaration ::=
  component identifier [ is ]
    [ local_generic_clause ]
    [ local_port_clause ]
end component [ component_simple_name ] ;

There's no place for signals in component declaration.

You'll later notice that your component declaration, besides unexpected signal declaration are also incomplete because they don't
declare all ports of the respective components.

We would e.g. expect

component rr_ip
  port(
    ninit_done : out std_logic
  );
end component;

Just to give you a starting point. You should have a VHDL text book or tutorial at hand.




 

[MATRIX7878]

Hello,

     Ok, I see where I am going wrong.  I still do not know where to (or rather what to declare) some of the variables as.  I have tried to figure out what I need to do for the Reset Release IP but cannot get it to work.  I do not know what should be a signal, a port, or something else.  I am attaching my new code and errors.  The Reset Release code is lines 13-27.  I hope this looks better.  I have tried to follow the tutorial for the Reset Release IP I found through Intel, but the code provided was pseudocode and I am still trying to figure out VHDL.

Thank you,

Drew

[Nurina]

Hello,

Seems to me that the Reset Release IP is correctly instantiated.

Based on the error message, the problem is due to the sys_pll component instantiation on line 26.

You were trying to connect to ports that do not exist in the sys_pll component.

Please check if the connections are correct. These threads may be helpful for you: https://www.edaboard.com/threads/problem-with-using-components-in-vhdl.374664/

https://community.intel.com/t5/Intel-Quartus-Prime-Software/Error-10349-VHDL-Association-List-error-at-mult16bit-vhd-41/m-p/94175

Regards,

Nurina

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

[MATRIX7878]

Hello,

     Alright, I think I took care of that issue, but now something new has happened.  I am getting an error saying that the IP may not work with my code.  Did I turn on the signals wrong, or does the IP need to be its own VHDL file?  I am attaching my code for review and the errors.

Thank you,

Drew

[FvM]

The error message tells you that your project misses implementation code for the two instantiated components.

[MATRIX7878]

Hello,

     I do not know what implementation is needed.  I moved the RRIP into its own .vhd file and now my top-level file is riddled with errors.  I simply cut and pasted all the RRIP code into a separate file and saved it into the same directory.  I gave it its own architecture and begin statements.  What else needs to be done?  All the errors are coming up as part of something else not working (ghost errors I call them).

Thank you,

Drew

[Nurina]

Hi,

Now your Reset Release IP VHDL file does not look like Reset Release IP at all.

Are the reset release IP and sys_pll the same? Why are you combining them?

The error message is saying that you need to have an entity for both RRIP and sys_pll.

You may find these useful:

https://fpgatutorial.com/vhdl-entity-architecture-library/

https://vhdlwhiz.com/entity-instantiation-and-component-instantiation/

https://nandland.com/entity-and-architecture/

Regards,

Nurina

[MATRIX7878]

Hello,

     It does not?  Dang it.  I just moved all the code I needed for RRIP into its own .vhd file.  I see what you mean though.  I think that I am trying to keep as close as I can to the example, I saw in the Intel Reset Release IP video.  It had the example I started with.  I need to take that as pseudo code and work from there.  What parts of the code (image attached) do I need to implement and what parts are already made in the IP itself?  Am I declaring too many things?  I think I am confusing many things together and am making too much code.  Is there an example I can use of non-pseudocode?

Apologies for this taking a long time to get into my head, I think I keep focusing on the wrong thing.

Thank you,

Drew

[FvM]

You didn't manage to write valid entity code for rr_ip and sys_pll. Apart from other details, the entity name has to match the instantiated name. E.g.
entity rr_ip ...

[MATRIX7878]

Hello,

     I did not do it right?  The component and entity have the same name.  Perhaps I am not seeing what you are saying.  Could you please tell me what lines are not right.  I have a rr_ip and resetRelease component and instantiation.  Do I not need both?

Thank you,

Drew

[FvM]

O.k., resetRelease.vhd (second screenshot) contains entity declaration, but many syntax errors. Obviously it has been never compiled.

Not intended to be exhaustive:
- each entity declaration needs its own library statement

- all signals used in the arcitecture must be declared, either as port or internal signal
- process needs begin statement
- signal assignment uses <= rather than => operator

- can't write port signals with direction "in" 

It seems to me that you filled architecture bodies with arbitrary signal assignments instead of implementing meaningful code function. I'd rather try to write entities that serve a useful purpose.

[FvM]

Regarding your other question, you don't necessarily need compoenent decalarations when instantiating VHDL entities, you can use
this syntax
u1: entity work.sys_pll instead of u1: sys_pll

Alos explained in the links given by Nurina

[MATRIX7878]

Hello,

     I decided to just dump all the RRIP I had and start from scratch as the program was giving me a headache.  I found out how to see the .vhd file in the RRIP and saw that I had a conflicting naming convention for the files.  That was probably some of the problems.  I am still going through the online training of Intel, but I have not gotten to everything yet.  I see the .vhd file associated with the RRIP has and see that it has an entity that deals with the ninit_done port.  I have re-written the reset release file with this new file in mind and the links you all have sent me.  I thought I could get the code right, but I still am not getting it.  I do not know why this is not clicking with me.  I also see that I had somehow mixed up a port.  Locked equals to locked, not the out clock.  I do not know why I saw that.  The code looks much cleaner now, but it is still riddled with errors.  I should get this by now, but I am not.  The code without the RRIP compiles without error but gets a severe warning of no RRIP in the program.  At this point, I am hoping someone has an actual file for RRIP.

Thank you,

Drew

[sstrell]

You don't show what errors you're getting now, but here are the many issues I see:

Where is the code for component clockdiv?

Why does sys_pll.vhd have a signal in its port list named my_reset?  I presume you added this in for some reason.  Assuming this is generated from an IP, you should not be editing the top-level code for the IP.  In the IP Parameter Editor, you should go to Generate -> Show Instantiation template and use the template there to instantiate the IP exactly as it's generated.  There is no reason to edit the top-level code for a generated IP.  For a basic PLL, there are only 4 signals: refclk and rst inputs, and locked and outclk_0 outputs.  What are sys_clk and rst_in since there is already outclk_0 and rst?  And why is locked bidirectional?  It's an output status signal from the PLL.  And there is no bidirectional logic in the core of an FPGA.  The component declaration should simply be (from the instantiation template):

COMPONENT sys_pll is

        PORT (refclk, rst: IN STD_LOGIC;

                        locked, outclk_0: OUT STD_LOGIC);

END COMPONENT;

ninit_done is an output of the reset release IP and yet you are connecting it to an input port in the toplevel, an input pin of the device, which makes no sense.  It should be connected to reset inputs of the instantiated components or used as a status indicator.  And what is sys_rst supposed to be doing?  You declare it and then it's not used anywhere.  The reset release IP should be used as just a status indicator that device initialization is complete.  You can use it as a reset signal, but it won't ever go low again during normal operation of the device so it can't be used as a warm reset.

If you're not using the locked signal of the PLL, just leave it out of the port map.  You're basically connecting a signal to itself when you say locked => locked, which makes no sense.

Speaking of port mapping, you have it backwards for the PLL.  The first signal name is the name of the component's port.  The signal after "=>" is the signal in this level of the design that the lower-level port is connecting to.  So your PLL instantiation should probably look like this:

u1: sys_pll PORT MAP (rst_in => my_reset, clk => clk, outclk_0 => iclk);

Even this isn't perfect because what is the point of clockdiv?  You can divide a clock using the PLL itself instead of needing oclk and iclk.

I highly suggest you check out some VHDL training: https://cdrdv2.intel.com/v1/dl/getContent/652842

[MATRIX7878]

Hello,

     The errors I get are coming from extraneous things.  The errors are being caused by one error in one file that infects other files.  The code that I know works as it compiles is now erroring out because of something in another file.  I am attaching the clockdiv file, so you know what it is.  sys_pll.vhd has the my_reset port because I need it for the equation in my process.  I have a feeling though that that is not right. 

      I generated the IP, but I never got any code from it.  I was unaware of that ability to take the template code.  I learned about the IP from the youtube video and added it into the project as shown but did not know that I could take code from it that way.  I thought it was a library that existed to help the compiler.  I did not know what the top-level code was as I have no basis to go off of for the IP.  So, the IP creates u0 and I need to make u1 for the sys_pll.  Ok, I can do that.  I copied the code the IP generated and I have:

u0 : component RRIP
port map (
ninit_done => CONNECTED_TO_ninit_done -- ninit_done.ninit_done
);

The CONNECTED_TO_ninit_done is not defined and is causing an error.  This is not a signal, so how do I define this?

sys_clk and rst_in are variables I saw in the RRIP video, so I thought that they were needed.  Perhaps I already have things defined and am creating redundant symbols.  I would not put that past me.  Locked is bidirectional as I saw it equaling itself i.e. locked => locked.  I took it as this is a bidirectional pin.

With ninit_done being an output pin, I was under the impression that I would need an input pin for it as well to give data to something.  If I cannot connect it to an input port, then I need an IF statement to say that it has changed?  Or is there something else I can do?

The sys_rst is the flag saying that the system has reset that I saw on the video.  Once I got my code running, I was going to use that as the checker to make sure the system reset.  I thought that that was the point of it.  I understand what the RRIP is supposed to do, but my ability to code it is far from perfect.

In the video they had the line locked => locked, so I thought that that was what I needed to do.  It did not make sense to me either, but I trusted the video as it was from Intel.  They should know their FPGA code is what I figured.

clockdiv is used for the main portion (sig.vhd) of the code to create a 25 MHz clock for the logic.  The code will run on a frequency of 25 MHz.

I think I am slowly getting this as it is starting to make more sense now.  

I did do the training, but it appears as though I need to go back through it.  Oh boy.  I am attaching the errors (meaningful errors) I am getting now and the code I have.

Thank you for your patience.  I am trying my best to get this.

Drew

[sstrell]

Lots happening here.

When you generate IP, it creates a number of files.  You just don't need to interact with them usually.  The generated code is placed in folders in your project directory (may be the instance name you gave to the IP or in an "ip" directory).  It looks like you took the top-level file generated by the PLL IP and edited it (adding my_reset) which you should not do.

The template includes "CONNECTED_TO_..." to indicate where you need to edit it to replace it with the appropriate connection in your design.  That's why it's just a template and not the final code you should be using.  

ninit_done is an output signal of the IP, not an actual hardware output pin of the device.  As such, you could certainly connect it to an output pin of the device to bring the signal out of the FPGA or connect it to the input of some other logic (like a reset input for example).  This does not mean you can connect it to an actual hardware input pin of the device.  As I stated previously, this makes no sense.

And as I suspected, clkdiv is not required.  It's not clear if you need one or two clock domains, but you could just use the PLL to create the divided clock instead.

[MATRIX7878]

Hello,

     I did not use the PLL IP.  The only IP I have is the Reset Release IP.  Is that what you are calling the sys_pll?  I did not know that that was to come from an IP.  I thought that that was its own code chunk.

     Can the template space be replaced with a signal?  It would then need to change the direction of the => to <= if I am not mistaken.  I do not think that making it ninit_done => ninit_done makes sense, so I need to create a new port for it.  Is that right?

     Ok, I think that the label is defined as a PORT and not a SIGNAL, so I might have misunderstood what it was trying to become.  Ah, I see what you are saying.  ninit_done is a software signal that talks within the software, it is not a hardware signal that I can connect to an LED.  I can connect it to another software pin that can trigger a hardware function to turn on an LED if I desire, but I cannot use the signal directly.  I think that was a big part of the problem I was having with understanding.

     clkdiv is needed at least for the LED and switch control of the main program.  That was the clock I had before I knew that I had to have a Reset Release.  It would probably be best to have two clock domains, one for the reset and one for the main program.

Thank you and hopefully Nurina, has finished with my .qar soon,

Drew

[Nurina]

Hi Drew,

Since this involves a few vhd files, can you share the .qar file of your project?

To generate this, go to Project>Archive project.

This is so that I can add the necessary code changes and you can review them.

Regards,

Nurina

[MATRIX7878]

Hello,

     Of course.  Please find attached my .qar for this project.  The project itself is so much easier than the RRIP part.  At least it seems to be.  I have yet to comment the code, but thanks to the structure of VHDL, it seems to be more self-explanatory.

Thank you,

Drew

[Nurina]

Hi Drew,

Is the sys_pll suppose to be just a PLL? Where did you get this code?

Based on line 15, you are latching the sys_rst with locked and rst but there is a syntax error due to locked being an output port of the sys_pll. I'm not sure what you wanted the sys_pll to describe.

I have resolved the errors and used an IOPLL IP in place of the sys_pll.vhd. You can make changes to the IOPLL settings as you wish. I'm attaching the .qar file here shortly.

Regards,

Nurina