Reset Release IP VHDL code not working

[MATRIX7878]

Hello,

     I am trying to create a simple VHDL design test for an Agilex 7 m-series FPGA and have hit a snag.  I am trying to create a Reset Release IP code snippet and cannot seem to figure out what to do.  I do not know what is declared in the IP itself and tried working with the code I saw on the RRIP video.  I am attaching my code and the errors I am getting.  Any help would be appreciated.

Thank you,

Drew

[Nurina]

Hi Drew,

Here is the .qar file with resolved code as promised.

You can check the RTL viewer to see if the connections were what you were intending.

I highly recommend these training videos since you're a beginner: 

https://www.youtube.com/watch?v=bwoyQ_RnaiA&

https://www.youtube.com/watch?v=lHowLUNHFFA&

The VHDL training link shared by strell is also very useful to go through.

Regards,

Nurina

[MATRIX7878]

Hello,

      It looks good in the RTL viewer.   Will need to run a simulation of course to make sure it works.  I am currently enrolled in the Intel training versions of those YouTube links you shared.

     While all the errors are gone, upon completing the Analysis and Synthesis step of compilation, I get the warnings attached in the image.  I look at the file that the 2nd warning references and it complains that the Reset Release is not there.  I'm confused.  Is the IP not started?  What do I need to do?  I am attaching the report file as well.  We were so close to me getting it.  Is it because I am using an Agilex 7 M-Series?  I would not see why.

Thank you for your continued support.  It means a lot to me.

Drew

[MATRIX7878]

Hello,

     I got this code from the Reset Release IP video I found on Intel's website and also on YouTube.  I was following the code that I saw on that video to get the sys_rst line.

     You used another IP?  Ok.

Thank you,

Drew

[Nurina]

Hi,

I checked and it's because toplevel.vhd is not set as top level entity.

Set the toplevel.vhd as top level entity and it will resolve the RES-10204 - Reset Release Instance Count Check warning.

Ultimately you should check the RTL viewer/simulation to see if this is the circuit/functionality you were going for.

Regards,

Nurina

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

[MATRIX7878]

Hello,

     That solves that problem, but there is the other error that I am attaching below.  I do not know why it says that the FPGA is not compatible.  It sounds to me that either the FPGA cannot get out of the RRIP, or it cannot find the registers to get in.  I am not sure which, if either.  That should be the last thing I need help with.

Thank you,

Drew

[Nurina]

Hi Drew,

I think you can ignore the Evaluation Mode warning. It doesn't seem like you're using it anyway. More info about it here: https://www.intel.com/content/www/us/en/docs/programmable/683502/17-1/an-320-using.html

You got those warnings because the reset release IP isn't connected to those registers, and in fact it isn't connected to anything in your project at all. I wasn't sure how you want to connect the reset release IP and I'm not an expert on this IP's usage. I was just helping out to fix the syntax errors.

What do you want to use this IP for? How do you want to connect it to the other modules?

You may find this useful: https://www.intel.com/content/dam/support/us/en/programmable/support-resources/bulk-container/pdfs/literature/an/archives/an891-19-3.pdf

Regards,

Nurina

[MATRIX7878]

Hello,

     I can ignore them?  Good to know.

     It is not connected, but it is included.  I see, I will need to see how to actually use it.  The only reason I even knew about the RRIP was because I got a critical warning about it.  Other than that, the project was fine.  I appreciate the help with the syntax errors.

     I am using the IP to reset the FPGA after the circuit is programmed.  I am not sure how I want to connect it to other modules.  I thought that maybe it would connect itself as the IP was connected.

     It seems like I need to go more in depth into that .pdf.

Thank you,

Drew

[Nurina · Accepted solution]

By the way, here is how your project netlist looks like in the RTL viewer. You should really check the connections and make sure if this is what you intended.

The connections are easily changed through portmapping as I had helped you earlier. You may check out the VHDL trainings as it covers this.

It seems like a very small project. What are you trying to do with this project? Are you just going to run simulations? Are you going to do hardware programming?

Regards,

Nurina

[MATRIX7878]

Hello,

     The RTL viewer looks to be correct.  That is what I would expect.  I do not see a need to change port mapping for the main part.  It is just the RRIP I need to connect somehow.

     It is a very small project indeed.  It is to mimic the taillights of a Ford Mustang.  The blinking of one after another.  For now, it is just simulations, as I do not have an actual board.  I cannot find the board I want with the Agilex 7 M-Series.  I am currently designing my own FPGA board around the aforementioned FPGA core and then I will program the hardware on that when I get it made.  For now though, it is just simulation until I get a physical board.

Thank you for all your help,

Drew

[sstrell]

You do realize that an Agilex 7 M-series would be waaaay overkill for something like this?  It's a brand new device and I'm sure dev kits for it will probably start around $10k.  I don't think dev kits are even available for it yet.

Even an Arria 10 or Cyclone 10 GX would be more than enough for a design like this.  And probably much less expensive.

[MATRIX7878]

Hello,

     Yes, I am aware.  I just wanted to start off with something simple as a design to test the waters if you will.  I plan on making much more complex designs later.  I do not plan on buying a dev kit and I have seen 2 as PCIe slot card dev kits.  I am planning on making my own FPGA board.  I need the Agilex 7 M-series as it has DDR5 and PCIe Gen 5 capabilities.  I need to use the modern standards so I can get more qualifications on my résumé.  I have a majority of the parts I want for the board already in my PCB schematic, I am just missing the brains.  I cannot find a model of the FPGA.  I want to use Quartus 1st to make sure that I at least know what I will need to do when I make the board.

Thank you though for making sure I was aware of what I was doing,

Drew

[Nurina]

Hi Drew,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Feel free to open a new thread or login to ‘ https://supporttickets.intel.com ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

If any answer from the community or Intel Support are helpful, feel free to rank your support experience by rating 4/5 survey. Please let me know of any inconvenience so that I may improve your future service experience.

Have a great day!

Best regards,

Nurina W.

[MATRIX7878]

Hello,

     Thank you for letting me know.  I'm glad that this could be resolved as well.  Now to figure out how to use the RRIP in the program.

Drew

[nadeem129aa]

 I do not know what should be a signal, a port, or something else.  I am attaching my new code and errors.  The Reset Release code is lines 13-27.  I hope this looks better.  I have tried to follow the tutorial for the Reset Release IP I found through Intel,

[sstrell]

Not seeing any attachments.