Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16935 Discussions

Simulating JTAG to Avalon

shaiko
New Contributor I
523 Views

Hello,

I'm using the JTAG to Avalon IP in my design.
In the lab, the IP will be controlled by a JTAG link.

But how can I simulate it ?
How can I provide it user stimulus in simulation ?
For example, generate a write command in simulation to address 0x0 ?

Labels (1)
0 Kudos
1 Reply
ShengN_Intel
Employee
482 Views

Hi,

 

You'll need to use BFM simulation. This tutorial document link https://forums.parallax.com/discussion/download/110606/altera_jtag_to_avalon_mm_tutorial.pdf under section 3.5.3 JTAG-to-Avalon-MM Master probably can clear your doubt.

Attached the tutorial design file jtag_to_avalon_mm.zip below for your reference. May refer to the example testbench sopc_system_jtag_master_tb.sv and execute the run_simulation.tcl with simulator.

Simulation result as below screenshot:

waveform.png

If you encounter compilation error in simulator, remember to temporarily comment out some lines (if else statements) in ../sopc_system/simulation/submodules/altera_avalon_st_jtag_interface.v like below screenshot in order for altera_jtag_sld_node (node) to link with sopc_system_jtag_master_tb.sv:

comment_out.png

 

Thanks,

Best Regards,

Sheng

 

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer.

Reply