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15380 Discussions

Simulation of PLL generated by Quartus with Modelsim

sugi
Beginner
462 Views

Hello,

 

When I generated the PLL with Quartus Prime Lite and simulated it with Modelsim, the PLL output c0, locked was "1'hz".

The correct clock waveform was confirmed for the PLL input inclk0. How can I get Modelsim to output correctly from c0, locked?

I uses v files for The source code , and I compile "pll.v", "pll_bb.v", "pll_alpll.v", "altera_mf.v" files in addition to the top module and testbench v files in Modelsim.

0 Kudos
7 Replies
EngWei_O_Intel
Employee
434 Views

Hi there

 

Do you run enough cycles for your simulation? Have you seen any warning/error during Modelsim compilation?

 

thanks.

Eng Wei

sugi
Beginner
419 Views

Hi,

 

I run enough cycles for simulation, but the PLL output c0, locked are "1'hz".

I have not seen any warning/error during Modelsim compilation.

Do I need to compile other files?

 

EngWei_O_Intel
Employee
406 Views

Hi 

 

Are all signals that you have seen a Z is at the same hierarchy as input inclk0? Are you seeing Z for all the signals at lower hierarchy or they are at Top level of testbench?

If you can share a sample example that would be good.

Thanks.

Eng Wei

EngWei_O_Intel
Employee
406 Views

In your modelsim script can you try to add below lines:

 

add wave /<your_testbench_top>/<your_top_design>/<your_signal_hierarchy_level>/*
view structure
view signals
run -all
sugi
Beginner
399 Views

Hi,

Thank you for the advice.

I added a line to the modelsim script, but it didn't change.

The source code is a simple one created for the PLL test.

The pll_generate module is set to divide the 50MHz input clock into 25MHz.

The simulation results are also attached.

 

Below source code

///////////////////////////////////////////////////

module test_pll(
CLK50M,
RESET
);

input CLK50M;
input RESET;
wire CLK25M_pll;
wire locked;

pll_generate U_pll_generate (
.areset (RESET ),
.inclk0 (CLK50M ),
.c0 (CLK25M_pll ),
.locked (locked )
);

endmodule

/////////////////////////////////////////////////

Below simulation result

pll_test.PNG

EngWei_O_Intel
Employee
378 Views

Hi there

 

Are you able to share your sample proj? Would like to look at your entire setup including the testbench.

 

Thanks. 

Eng Wei

EngWei_O_Intel
Employee
325 Views

Hi there


Since there's no response from you to the previous reply that have been provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Eng Wei


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