When I generated the PLL with Quartus Prime Lite and simulated it with Modelsim, the PLL output c0, locked was "1'hz".
The correct clock waveform was confirmed for the PLL input inclk0. How can I get Modelsim to output correctly from c0, locked?
I uses v files for The source code , and I compile "pll.v", "pll_bb.v", "pll_alpll.v", "altera_mf.v" files in addition to the top module and testbench v files in Modelsim.
Thank you for the advice.
I added a line to the modelsim script, but it didn't change.
The source code is a simple one created for the PLL test.
The pll_generate module is set to divide the 50MHz input clock into 25MHz.
The simulation results are also attached.
Below source code
pll_generate U_pll_generate (
.areset (RESET ),
.inclk0 (CLK50M ),
.c0 (CLK25M_pll ),
.locked (locked )
Below simulation result
Since there's no response from you to the previous reply that have been provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.