Splitting SOPC DDR2 control signals to top and bot- cyclone III

[Altera_Forum]

Hi all, 

 I want to use onboard DDR2 SDRAMs on Cyclone 3 development kit (i want to use 64 bit). I designed all SOPC stuff with DQ width 64 (I changed DQ width in modify parameters option of DDR2 sdram controller to 64 in SOPC). I have two questions:   1)Local interface width became 128 after I changed DQ width to 64 in SOPC. Is this what I might wanna see? 2) This is the more crucial question. SOPC module has only one output for each control signal (cas, ras, cs, etc.). When tried to split them in the top module, I get error saying signal-splitters have invalid fanouts. How can I distribute the output control signals to bot and top banks, or is there a way to make SOPC output two of them ?   Pls. try to explain clearly the advanced statements, I am new in Quartus :)

[Altera_Forum]

Is there no one to help me ? :confused:

[Altera_Forum]

Hi! I'm having the same problem. Were you able to find a solution? 

 Thanks!

[Altera_Forum]

Unfortunately no, I would expect some solutions here in this forum. If you somehow can figure it out, please drop a line here. 

 Thanks

[Altera_Forum]

I ended up giving up and using the two banks (top and bottom) seperately. I don't it's possible to use all the DDR as one memory bank.

[Altera_Forum]

I have no experience with SOPC. But maybe you can try this: edit the toplevel file generated by SOPC, assign intermediate signals to the ports of the ddr2 controller you want to double up and connect the intermediate signals further to the output pins. Something like this:signal lcas_n : std logic ... port map ( ... ddr2_cas_n => lcas_n , ... ) ; Cas1_n <= lcas_n ; Cas2_n <= lcas_n ;

[Altera_Forum]

josyb, 

 I've been using Verilog and putting the system together manually. The top and bottom control signals cannot be combined and this seems to be a common problem. The board's reference manual never mentions that all the SDRAM can be used at once:  "The data bus can be configured as two separate buses of 32 bits each, or a single 32-bit and a single 40-bit bus." [p. 2-47]  I take this to mean that using the SDRAM as a single, 72 bit wide bus is not possible.

[Altera_Forum]

I'd say if you can use two separate buses of 32 bits and 40 bits, it should be possible to drive them as a (combined) single 72 bit bus. 

I'll have to look in the documentation of the development board(s) you are using. Tell me which one?

[Altera_Forum]

I'm using the cyclone III development board. 

 The problem is that the control signals are split between the top and bottom memory "banks". Combining them causes errors during compilation.   Also, confusion is created by the preset available for a 72 bit memory bus which exists in the DDR2 HPC megafunction wizard. It simply doesn't work.

[Altera_Forum]

I had a quick look in the "Cyclone III Development Board Reference Manual" and it looks to me that driving it as a single 72 bit RAM should entirely be possible. 

I'm not that fluent in Verilog , but send me a .qar and I will give it a try.

[Altera_Forum]

I've had the reverse problem...  

I'm working on a Cyclone III Development Board and am trying to figure out how to use the DDR2 high speed controller and use the SDRAM as separate top and bottom banks. I'm working in Quartus II 9.1 sp2 with SOPC builder. The documentation clearly states the SDRAM can be used in separate banks or as a single bank I haven't found anywhere where it talks about how to separate them.   I also am looking for a good starting point "standard design" and found the "standard" files included with the Cyclone III board CD are missing many components.   How do I separate the SDRAM into top and bottom banks in SOPC builder?  Do I need a MM clock bridge or tri-state bridge? Have any of you found a good starting point for a new design?  Thanks!