State machine unstable

[Altera_Forum]

Hi, 

 I'm sort of new to Verilog (only used it for a few months) but I have worked with HW and SW design for a long time. Verilog seemed fun and I went ahead to try it on a cool project.  http://rosenborg.homelinux.org/wp/?cat=4  However, I do experience problems. I use a state machine in the graphics board to control reading and writing pixel data, sprite position and other settings etc. I have a 512k 10ns RAM and three 8-bit D/A ladders connected. And it is working kind of well. The problem is it is unstable. Sometimes when I compile I get a result that works exactly as I intend. Then, if I only change some small detail, like the init value of a register, I get a result that "crashes" as soon as it is started or when I perform some sort of action, like uploding data to the RAM. Of course, when I change something in the code and re-compile, even the smallest changes affect how gates are placed in the FPGA, and I guess this somehow gives me problems.  It says it can run my design at 115MHz, and I run at 100MHz, so it should be ok. I'm using about 50% of the gates and 90% of the RAM.   Whet in "crashes" it seems like all activity in the main state machine stops. Like if the state is changed to an unused state and then it hangs there. It does not help to add code to force the state variable back to a known state using a button, for example. Other stuff in the same always block runs as it should even after a crash.  So, as a beginner, I'm hoping there are some beginner mistakes I have made. If you have an idea, please point me in the right direction.  Best regards, Jonas

[Altera_Forum]

hi, 

my experience is that state machines get unstable if controlling Input signals are not synchronized with FSM clock... Maybe you are facing similar effects?

[Altera_Forum]

This sounds very much like a timing problem or problem with asynchronous logic somewhere. Do you have proper timing specs? Do you have some logic that is not synchronised to the system clock. 

 If you have asynchronous logic you are luck to get the fitter to give you a placement that doesnt violate some timing relationship. The seed value for the fitter changes on every change on source code (ANY chance completly changes the seed) or fitter seed (set via the project settings).  Are all signals synchronous to the main clock? are there any paths that you havent synchronised?

[Altera_Forum]

Hi Jones, 

 As you know Verilog coding is running parallel and no sequential. What I could suggest is make sure each state you added in the correct condition and remember set the default state to prevent it to jump to unknown status. For debug purpose you can added a timer to monitor which state fail.  Regards, WaiMun     --- Quote Start ---  Hi,  I'm sort of new to Verilog (only used it for a few months) but I have worked with HW and SW design for a long time. Verilog seemed fun and I went ahead to try it on a cool project.  http://rosenborg.homelinux.org/wp/?cat=4  However, I do experience problems. I use a state machine in the graphics board to control reading and writing pixel data, sprite position and other settings etc. I have a 512k 10ns RAM and three 8-bit D/A ladders connected. And it is working kind of well. The problem is it is unstable. Sometimes when I compile I get a result that works exactly as I intend. Then, if I only change some small detail, like the init value of a register, I get a result that "crashes" as soon as it is started or when I perform some sort of action, like uploding data to the RAM. Of course, when I change something in the code and re-compile, even the smallest changes affect how gates are placed in the FPGA, and I guess this somehow gives me problems.  It says it can run my design at 115MHz, and I run at 100MHz, so it should be ok. I'm using about 50% of the gates and 90% of the RAM.   Whet in "crashes" it seems like all activity in the main state machine stops. Like if the state is changed to an unused state and then it hangs there. It does not help to add code to force the state variable back to a known state using a button, for example. Other stuff in the same always block runs as it should even after a crash.  So, as a beginner, I'm hoping there are some beginner mistakes I have made. If you have an idea, please point me in the right direction.  Best regards, Jonas  --- Quote End ---  

[Altera_Forum]

Hi Jonase, 

 As you mention "It says it can run my design at 115MHz, and I run at 100MHz, so it should be ok. I'm using about 50% of the gates and 90% of the RAM". Is really a timing issue, are you able to do some timing analysis, and confirm which path have a longest path that fail setup and hold time.