Stratix 10 512 Bits AST2AVMM Example Design

[danield17]

Hi,

Is anyone familiar with this example design?
It appears in the IP Catalog even when the device family I have chosen is Agilex 7.
I wonder if there is any documentation about this IP and whether I can use it for Agilex 7, even though its name is "Stratix 10 512 bits...".

I am looking for an easy way to convert the Avalon Streaming interface of the "F-tile Avalon Streaming IP for PCIe" to an Avalon Memory-Mapped interface for each BAR, similar to how it is implemented in the PCIe Avalon Memory-Mapped IP cores of Arria, Cyclone, and Stratix.

Regards,
danield17

[ventt]

Hi danield17,

Thanks for reaching out.

Allow me some time to investigate your issue. I shall come back to you with the findings.

Thanks.

Best Regards,

Ven

[ventt · Accepted solution]

Hi danield17,

My apologies for the late response.

After searching and checking with the team, I am afraid to say that there is no documentation available dedicated to this IP. Only a short functional description of this IP can be found in the Example Design User Guide. This IP is designed purposely to accommodate the Stratix 10 Avalon-ST PCIe Example Design. Therefore, please bear in mind that it has not been validated on all devices. 

Hence, this IP cannot be directly ported into your design for use. Note that the PCIe Base Specifications supported on both devices are different. Additionally, please take note of the differences in the TLP header and data alignment handling between the two devices. If you want to port this IP to Agilex 7 F-Tile, you must make necessary modifications to compensate for these changes. 

Refer to User Guides:

1. Intel® Stratix® 10 Avalon® Streaming (Avalon-ST) IP for PCIe* Design Example User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683361/17-1/functional-description-for-pio-design.html

2. F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683140/25-1/tlp-header-and-data-alignment.html

3. L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide: https://www.intel.com/content/www/us/en/docs/programmable/683111/23-4/tlp-header-and-data-alignment-for-the.html

Again, I apologize for my late updates. Please let me know if you have any further questions.

Thanks.

Best Regards,

Ven

[ventt]

Hi danield17,

Thank you for your confirmation and response in accepting the solution.

I am glad that your questions have been addressed.

With that, I will transition this thread to community support. If you have a new question, feel free to open a new thread to get support from Altera experts.

Thanks.

Best Regards,

Ven