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Altera_Forum
Honored Contributor I
936 Views

Suggesting a testbench for a design

Hello everyone, I have a simple (4x1) multiplexing system in VHDL that consists of the following files: 

 

I would really be grateful if someone could provide me with a possible testbench. I can successfully Simulate the design using quartus ii simulator but I want to use (modelsim- altera) which requires a testbench. Thanks for your hlep.  

 

 

 

1) 

------------- VHDL description for a 4x1 Multiplexer ---------------------------- 

 

 

 

 

library ieee; 

use ieee.std_logic_1164.all; 

entity mux4 is 

port (  

I : in std_logic_vector (3 downto 0); 

reset: in std_logic; 

s : in std_logic_vector (1 downto 0); 

y : out std_logic); 

end mux4; 

architecture behavior of mux4 is 

begin 

Design: process (reset,I,s) 

begin 

if reset = '0' then 

y <= '0'; 

elsif s = "00" then 

y <= I(0); 

elsif s = "01" then 

y <= I(1); 

elsif s= "10" then 

y <= I(2); 

else 

y <= I(3); 

end if; 

end process; 

end behavior; 

 

-------------------------------------------------------------------------------------------------- 

 

2) 

 

---------------------- Frequency division by 2 ----------------------------------------- 

LIBRARY ieee; 

USE ieee.std_logic_1164.all; 

----------------------------------------- 

ENTITY freq_div2 IS 

PORT ( clk : IN STD_LOGIC; 

out2 : BUFFER STD_LOGIC); 

END freq_div2; 

----------------------------------------- 

ARCHITECTURE example OF freq_div2 IS 

BEGIN 

PROCESS (clk) 

VARIABLE count2 : INTEGER RANGE 0 TO 7; 

BEGIN 

IF (clk'EVENT AND clk='0') THEN 

count2 := count2 + 1; 

IF (count2 = 1) THEN 

out2 <= NOT out2; 

count2 := 0; 

END IF; 

END IF; 

END PROCESS; 

END example; 

---------------------------------------------------------------------------------------------- 

 

3) 

 

---------------------- Frequency division by 4 ------------------------------------------- 

LIBRARY ieee; 

USE ieee.std_logic_1164.all; 

----------------------------------------- 

ENTITY freq_div4 IS 

PORT ( clk : IN STD_LOGIC; 

out4 : BUFFER STD_LOGIC); 

END freq_div4; 

----------------------------------------- 

ARCHITECTURE example OF freq_div4 IS 

BEGIN 

PROCESS (clk) 

VARIABLE count4 : INTEGER RANGE 0 TO 7; 

BEGIN 

IF (clk'EVENT AND clk='0') THEN 

count4 := count4 + 1; 

IF (count4 = 2) THEN 

out4 <= NOT out4; 

count4 := 0; 

END IF; 

END IF; 

END PROCESS; 

END example; 

------------------------------------------------------------------------------------------ 

 

4) 

---------------------- Frequency division by 6 -------------------------------------- 

LIBRARY ieee; 

USE ieee.std_logic_1164.all; 

----------------------------------------- 

ENTITY freq_div6 IS 

PORT ( clk : IN STD_LOGIC; 

out6 : BUFFER STD_LOGIC); 

END freq_div6; 

----------------------------------------- 

ARCHITECTURE example OF freq_div6 IS 

BEGIN 

PROCESS (clk) 

VARIABLE count6 : INTEGER RANGE 0 TO 7; 

BEGIN 

IF (clk'EVENT AND clk='0') THEN 

count6 := count6 + 1; 

IF (count6 = 3) THEN 

out6 <= NOT out6; 

count6 := 0; 

END IF; 

END IF; 

END PROCESS; 

END example; 

----------------------------------------- 

 

5) 

---------------------- Frequency division by 12 ------------------- 

LIBRARY ieee; 

USE ieee.std_logic_1164.all; 

----------------------------------------- 

ENTITY freq_div12 IS 

PORT ( clk : IN STD_LOGIC; 

out12 : BUFFER STD_LOGIC); 

END freq_div12; 

----------------------------------------- 

ARCHITECTURE example OF freq_div12 IS 

BEGIN 

PROCESS (clk) 

VARIABLE count12 : INTEGER RANGE 0 TO 7; 

BEGIN 

IF (clk'EVENT AND clk='0') THEN 

count12 := count12 + 1; 

IF (count12 = 6) THEN 

out12 <= NOT out12; 

count12 := 0; 

END IF; 

END IF; 

END PROCESS; 

END example; 

----------------------------------------- 

 

 

6) 

---------------------- Frequency division by 24 ------------------- 

LIBRARY ieee; 

USE ieee.std_logic_1164.all; 

----------------------------------------- 

ENTITY freq_div24 IS 

PORT ( clk : IN STD_LOGIC; 

out24 : BUFFER STD_LOGIC); 

END freq_div24; 

----------------------------------------- 

ARCHITECTURE example OF freq_div24 IS 

BEGIN 

PROCESS (clk) 

VARIABLE count24 : INTEGER RANGE 0 TO 15; 

BEGIN 

IF (clk'EVENT AND clk='0') THEN 

count24 := count24 + 1; 

IF (count24 = 12) THEN 

out24 <= NOT out24; 

count24 := 0; 

END IF; 

END IF; 

END PROCESS; 

END example; 

----------------------------------------------------------------------------------- 

 

 

 

 

 

 

7) 

 

 

------- Creating a package named (my_component) ------------------------- 

 

 

LIBRARY ieee ; 

USE ieee.std_logic_1164.all ; 

USE ieee.std_logic_unsigned.all ; 

package my_component is 

component freq_div2 is 

port( 

clk : in STD_LOGIC; 

out2 : buffer STD_LOGIC 

); 

end component; 

component freq_div4 is 

port( 

clk : in STD_LOGIC; 

out4 : buffer STD_LOGIC 

); 

end component; 

component freq_div6 is 

port( 

clk : in STD_LOGIC; 

out6 : buffer STD_LOGIC 

); 

end component; 

component freq_div12 is 

port( 

clk : in STD_LOGIC; 

out12 : buffer STD_LOGIC 

); 

end component; 

component freq_div24 is 

port( 

clk : in STD_LOGIC; 

out24 : buffer STD_LOGIC 

); 

end component; 

component mux4 is 

port (  

I : in std_logic_vector (3 downto 0); 

s : in std_logic_vector (1 downto 0); 

reset: in std_logic; 

y: out std_logic); 

end component; 

end my_component; 

 

----------------------------------------------------------------------------------------------- 

 

 

 

 

 

8) 

 

 

 

 

------------- Top-level structural description for the multiplexing system ----------- 

 

 

LIBRARY ieee ; 

USE ieee.std_logic_1164.all ; 

USE ieee.std_logic_unsigned.all ; 

use work.my_component.all; 

entity Mul_sys is 

port (clk, reset : in std_logic; 

y : out std_logic); 

end Mul_sys; 

architecture structural of Mul_sys is 

signal n : std_logic_vector(4 downto 0);  

begin 

u0: freq_div2 port map (clk =>clk, out2 => n(0)); 

u1: freq_div4 port map (clk =>clk, out4 => n(1)); 

u2: freq_div6 port map (clk =>clk, out6 => n(2)); 

u3: freq_div12 port map (clk =>clk, out12 => n(3)); 

u4: freq_div24 port map (clk =>clk, out24 => n(4)); 

u5 : mux4 port map (I(0) => clk, I(1) => n(0), I(2) => n(1), I(3) => n(2), s(0)=> n(3), s(1)=> n(4), reset =>reset, y => y); 

end structural;
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2 Replies
Altera_Forum
Honored Contributor I
24 Views

Hello 

You can look on the internet for books about fpga 's by pong chu. 

In the VHDL versions, look for the term testbench. 

You will find nice examples there. 

The older book releases can be found online for free. 

Best Regards, 

Johi.
Altera_Forum
Honored Contributor I
24 Views

Reply