Re: Synthesis switch for .sdc ?

Altera_Forum · ‎06-28-2011

Hello everybody

I'm using VHDL constant definitions and generate statements to synthesize two different use cases of my FPGA. With growing complexity, the number of warning messages, caused by timing constraints working on the currently not present parts, is getting somwhow annoying (and may prevent from noticing real problems).

I wonder, if there is a kind of "Compile Switch" (IFDEF or similar) for .sdc files (ideal case would be selecting the constraints directly based on my VHDL constants, however a separate switch in the begginning of .sdc might fit as well).

Any hints?

Regards,

Peter

Altera_Forum · ‎06-28-2011

SDC files are in fact Tcl code, so you can use standard Tcl programming to put decisions in your code. You have to be careful though because TimeQuest doesn't not digest all statements well, e.g. the 'post_message' will upset the synthesiser and prevent it from doing 'timing driven synthesis'.


set family "Cyclone II"
...
if {$family == "Cyclone II"} {
	set pllclk0 "pll|altpll_component|pll|clk"
	set pllclk1 "pll|altpll_component|pll|clk"
	set pllclk2 "pll|altpll_component|pll|clk"
} else {
	if {$family == "Cyclone IV E"} {
		set pllclk0 "pll|altpll_component|auto_generated|pll1|clk"
		set pllclk1 "pll|altpll_component|auto_generated|pll1|clk"
		set pllclk2 "pll|altpll_component|auto_generated|pll1|clk"
	}
}
...
set_input_delay -clock $pllclk0 -max 1.5 Writing

I too share your concern for zero-warnings (I wish Altera's IP-designers would too), as "a warning is an error waiting to happen". I heard this quote over 20 years a go, in a discussion over the then at-that-time very 'loose' C-programming

Altera_Forum · ‎06-28-2011

Thanks, works pretty well...