Synthesizing design for PAC with Arria 10 GX fails

[RBash]

I'm trying to synthesize a design for a PAC with Arria 10 GX, but get the following messages when the synthesis script finishes. Since the error message doesn't give any particular information, I don't know where to look for issues to fix. It is especially confusing because first it's printed that "Info: Successfully synthesized partition", and then it fails (although I get another variation of this for a bigger design in which the partition isn't successfully synthesized). I expect the design to use 30%-40% of the ALMs on the Arria 10 FPGA, so I doubt that the design can't fit.

I use Quartus 17.1, and use "afu_synth_setup" to create the build directory and then inside that directory run "run.sh". I can synthesize other designs, and even some other variations of the same design successfully, so I don't think it's an environment or software version issue.

What am I missing here? Any help would be appreciated.

Info (17049): 272433 registers lost all their fanouts during netlist optimizations. Info (21057): Implemented 247070 device resources after synthesis - the final resource count might be different Info (21058): Implemented 2341 input pins Info (21059): Implemented 2621 output pins Info (21061): Implemented 210572 logic cells Info (21064): Implemented 31456 RAM segments Info (21062): Implemented 80 DSP elements Info: Successfully synthesized partition Info: Saving post-synthesis snapshots for 1 partition(s) Error: Quartus Prime Synthesis was unsuccessful. 1 error, 1768 warnings Error: Peak virtual memory: 17417 megabytes Error: Processing ended: Mon Apr 6 08:54:36 2020 Error: Elapsed time: 00:22:31 Error: Total CPU time (on all processors): 00:36:43 Info (19538): Reading SDC files took 00:03:57 cumulatively in this process. ------------------------------------------------ ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.   while executing "execute_module -dont_export_assignments -tool syn" (procedure "synthesize_persona_impl" line 14) invoked from within "synthesize_persona_impl $synth_rev" (procedure "compile_pr_revision" line 18) invoked from within "compile_pr_revision $options(impl)" (procedure "main" line 110) invoked from within "main" invoked from within "if {($::quartus(nameofexecutable) == "quartus") || ($::quartus(nameofexecutable) == "quartus_pro") || ($::quartus(nameofexecutable) == "qpro")} { #..." (file "./a10_partial_reconfig/flow.tcl" line 1039) ------------------------------------------------ Error (23031): Evaluation of Tcl script ./a10_partial_reconfig/flow.tcl unsuccessful Error: Quartus Prime Shell was unsuccessful. 7 errors, 1770 warnings Error: Peak virtual memory: 803 megabytes Error: Processing ended: Mon Apr 6 08:54:42 2020 Error: Elapsed time: 00:22:55 Error: Total CPU time (on all processors): 00:37:33 Quartus build failed

[JohnT_Intel]

Hi,

I observed that the Quartus Synthesis failed. Could you provide the full report log?

[RBash]

Thank you for your quick response. The log is attached.

[JohnT_Intel · Accepted solution]

Hi,

Thanks for the report file. It looks like there is a conflict on the your Quartus design where the IP name use is the same.

Below is the error message when Quartus Synthesis is performed. You will need to make some changes on your design so that it is not using the same file name.

Error (19021): The same file name "mm_bridge_0" is used for different IP files. The same name cannot be used for more than one IP file.

[RBash]

I see, thanks a lot for your help. I'll try that and will report the result here.

[RBash]

The synthesis is successfully past that stage, thanks again for your help.

[JohnT_Intel]

Glad to be able to help you

[RBash]

Hi John,

I was wondering if you could help me with another similar synthesis failure. This one is in a bigger design (although I still expect it to use ~60% of ALMs), and I don't have any IP files with the same name. I looked for the error you had found in the previous log, and it wasn't present in the log.

Thanks in advance.

[JohnT_Intel]

Hi,

From the error message, it failed to synthesis the partition. You might need to try out each to compile each of your partition or module.

[RBash]

Thank you for your response. The steps I take now are the following:

$ afu_synth_setup --source=rtl/filelist.txt build_fpga $ cd build_fpga/ $ $OPAE_PLATFORM_ROOT/bin/run.sh

So what you suggest is I compile each of my .qsys files manually using Quartus instead? And then how do I combine them all to generate a programming bitstream? Can you please point me to a document on how to do that if there exists one?

Thanks.

[JohnT_Intel]

I have no detail of the failure as the rpt file you provided only shows synthesis failure without any detail information. Not sure if you have synthesis each of the design previously?

[RBash]

No I didn't synthesize each module previously. The only thing I do before the three commands I mentioned is to generate HDL for the .qsys systems I have. If any particular file in the build directory would be helpful, I can upload that as well.

[JohnT_Intel]

Maybe you can provide me your project so that I can try out from my side. You can send it through private message if this is not appropriate to be attach into the forum

[RBash]

Thanks, that would be great. I just sent you a private message with the project.

[JohnT_Intel]

Hi,

Thanks for providing the project. I am able to performed Quartus Synthesis without any issue. May I know what is the system RAM that you are using?

[RBash]

Hi,

Thank you for following up. The system has 128GB RAM.​

[JohnT_Intel]

Hi,

That should be sufficient as I am only using 64GB system. Not sure how many have you tried?

[RBash]

Do you mean how many synthesis jobs? It's only this one, I ran nothing else with it. Is there a parameter for memory usage or other settings that I need to set correctly?

[JohnT_Intel]

No, do you try to recompile your design again? I am able to fully compile the design.

[RBash]

Yes, I have tried multiple times but the same error appears. In case this information helps, I have a Xeon Skylake Gold 6140M CPU, an Intel S2600WF server, and the OS is CentOS 7.6.

[JohnT_Intel]

Hmm, just to confirm the project that you provided is with the latest design right? Not sure if you are able to compile the design that you provided to me?