- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
How can I get this piece of code to compile?
This works fine in other synthesis tools, simulation etc. Just trying to map it to an FPGA. In Quartus 17.1 and 18.0 I get this error:
Error(13411): Verilog HDL syntax error at blah.sv(329) near text generate
Error(13224): Verilog HDL or VHDL error at blah.sv(329): SystemVerilog 2009 keyword generate used in incorrect context
generate
for (genvar i=0; i<N; i++)
for (genvar j=0; j<10; j++)
assign status = status_ff];
endgenerate
Any help will be appreciated. Thanks!!
- Tags:
- FPGA Design Tools
Link Copied
2 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I don't think I've seen the genvar commands inside the loop before. Try putting genvar i and genvar j above the generate keyword. You might also want to try inserting begin/end around the inner for loop. And how and where is N defined?
Also, why are you using generate for simple assignments? Can't you just use a normal for loop?- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Usually when you get an unexplainable syntax error, there is a problem with the code just before it.
SystemVerilog added the ability to put the genvar inside the for loop. Verilog-2005 made the generate/endgenerate keywords optional. The compiler should be able to tell from the context whether the for-loop is a generate-for or a procedural-for. I would try removing them and seeing if you get a different error message.
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page