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Quartus 13 Synthesis has the limitation that interface attributes cannot be used conveniently in a module. I am looking for a work around as this limitation does not appear in other tools.
Given a simple SV interface definition:interface avalon_bus
#(
parameter ADDR_WIDTH = 16,
parameter DATA_WIDTH = 8
)
(
input logic clock,
input logic reset
);
// aliais/short-cut for address and data widths
localparam AW = ADDR_WIDTH-1;
localparam DW = DATA_WIDTH-1;
localparam MaxAddress = 2**ADDR_WIDTH;
logic address;
logic writedata;
logic readdata;
modport per (
input clock,
input reset,
input address,
input writedata,
output readdata
);
endinterface
and a module that uses the interface: module avalon_mux
(
interface bus
);
localparam AddrThreshold = bus.MaxAddress/2;
logic pipe_a, pipe_b;
always @(posedge bus.clock) begin
if (busin.address <= AddrThreshold) begin
pipe_a <= bus.writedata;
end else begin
pipe_b <= bus.writedata;
end
end
endmodule
Quartus throws errors because it does not like the use of the "hierarchy separator" in most expressions. Does anyone know of a work around? Example, is there another way to express / localparam AddrThreshold = bus.MaxAddress/2 /? I have tried / const integer / and some other hacks but no luck, yet :( I have also attached an example Quartus project. Regards, Chris
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TO_BE_DONE
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Yes, something odd did happen. Your original post is no more!
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Might it magically reappear or do I have to recreate the post?
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Probably recreate it.
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No it didn't disappear, it was automatically moderated down by the forum's overzealous spam detection system.
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This is legal, but many not be supported by Quartus yet.
Try a continuous assignmentint AddrThreshold;
assign AddrThreshold = bus.MaxAddress/2;
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I was pleasantly surprised the continuous assignment worked
for the /AddrThreshold/ expression. But it doesn't work for the other uses cases, like:
logic pipe_a, pipe_b;
Best I can tell, I wont be able to use the parameters that are part of the interface. I will need to reduplicate all the parameters to the module:
module avalon_mux
# (
MaxAddress = 16,
DW = 16
)
(
interface bus
);
localparam AddrThreshold = MaxAddress/2;
logic pipe_a, pipe_b;
always @(posedge bus.clock) begin
if (busin.address <= AddrThreshold) begin
pipe_a <= bus.writedata;
end else begin
pipe_b <= bus.writedata;
end
end
endmodule
And then instantiate like:
avalon_mux
# (MaxAddress=bus.MaxAddress, DW = bus.DW)
M1(bus);
which partially defeats the purpose of using interfaces. Regards, Chris

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