Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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create different clocks at Test Bench

Altera_Forum
Honored Contributor II
1,174 Views

Hi ,  

i create 2 different clocks at Test Bench :  

1. clk_25M - clk_period = 1/25 MHz = 40 nsec 

1. clk_100M - clk_period = 1/100 MHz = 10 nsec 

 

At Model Sim I see correct wave of clk_25M . 

 

The wave of clk_100M is wrong , the wave start at '0' and after 45 nsec rise to '1' and after 45 nsec fall to '0' for 5 nsec and repeate .  

 

why is that ?  

 

Test Bench file and waves pictures attached .
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Altera_Forum
Honored Contributor II
465 Views

thats because the 100 MHZ clock wont change until after the 25MHz clock has changed. You need to put the two clocks in separate processes.

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Altera_Forum
Honored Contributor II
465 Views

Thanks , i learned new thing .

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