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Valued Contributor III
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SystemVerilog "unique if" not supported in Quartus?

It seems like Quartus 16.0 will choke on SystemVerilog "unique if" statements. Could somebody else confirm this, or are there additional SystemVerilog options which can be set in order to support it? 

 

Thanks!
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Valued Contributor III
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Q16.0 only supports the following SV constructs: 

http://quartushelp.altera.com/16.0/index.htm#hdl/vlog/vlog_list_sys_vlog.htm
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Valued Contributor III
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Quartus Prime Pro(which I believe only supports Arria 10) has a new front end HDL interpreter that supports a lot more than the old one. I don't have exact details on what it supports, but would expect this to be supported.

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Valued Contributor III
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--- Quote Start ---  

Q16.0 only supports the following SV constructs: 

http://quartushelp.altera.com/16.0/index.htm#hdl/vlog/vlog_list_sys_vlog.htm 

--- Quote End ---  

 

 

Thanks! 

 

That says "Supported (unique/priority supported only on case statements)" which basically means that unique if is not supported.
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Valued Contributor III
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Good point. I'll have to check that out.

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