TCL Macro for Top-Level Schematic to Verilog Conversion (For ModelSim Simulation)

[Altera_Forum]

I put together a little TCL script that automatically converts a schematic top-level entity to Verilog to help streamline preparation for ModelSim.  

 (This script improves the native Quartus b2v conversion tool and automatically swaps out the top-level for you.)   I put together a blog post talking about it here: http://idle-logic.com/2012/06/09/tcl-macro-for-top-level-schematic-to-verilog-conversion-for-modelsim-simulation/  I thought I might share it on the Altera Forums to reach a wider audience of people who might be interesting in this type of script.  --Chris

[Altera_Forum]

Cool. Note that the inst# can be changed directly in the schematic, just right-click on a symbol and go to properties and change it there.  

Rather than having the .qsf source the .tcl file directly, you can make it a pre-flow script, so that it runs at the beginning of a compile. (There are other posts). This might make for a good alterawiki page, with a link to your script, so others who do this flow could add their thoughts. Just an thought.

[Altera_Forum]

Thanks for the feedback Rysc. I just tried out your tip and I see how it totally improves the b2v inst# naming, very nice.  

 I like the pre-flow script idea, putting the "source b2vFixer.tcl" in the .qsf seemed to work, but it seemed a little kludgy having to hand edit this file.  When I have some more time I'll try putting together an alterawiki page for it.