Tcl error: ERROR: Argument <clk_object> is a collection with more than one object.

[SiWu]

Hi all, I am using cyclone 10 GX 10cx220YF780E5G to design LVDS SERDES, when the compilation flow goes to Timing Analysis step, it has an error message: Tcl error: ERROR: Argument is a collection with more than one object. I don't add any SDC file and tcl file. I acttached my project. I really don't know how to fix it. Can anyone help me figure it out? Thanks.

[SiWu]

I forgot to tell you that I use Quartus Prime Pro 23.4.0.79.

[TingJiangT_Intel]

Hi there, I tried your design and after I add the following constraint to SDC file, your design can pass the process:

derive_pll_clocks -create_base_clocks

[SiWu]

Thank you so much!

[TingJiangT_Intel]

 I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.