Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17268 Discussions

Tcl error while generating functional simulation Netlist

Altera_Forum
Honored Contributor II
1,437 Views

Hello, 

I was trying the generate the "General Functional Simulation Netlist" and I got this error message as below 

 

Error: Tcl error: can't unset "::quartus(qip_path)" no such element in error while executing 

"unset::quartus(qip_path)" 

 

What is the error message telling me?
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
723 Views

Do you have .qip files in your design? (Quartus IP files). They basically bundle all the IP files(i.e. I'm looking at a QSYS project with over 50 files, all added this way so the user doesn't have to manually manage them). If you look inside, the syntax used is something like so: 

 

set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) submodules/pci.v] 

 

The $ does variable substitution in Tcl. So $::quartus(qip_path) substitutes the hierarchy path to the .qip file. So wherever the user has the .qip file, as long as there is a /submodules/pci.v from it, it will find it. It allows all the IP to be bundled, moved around, added to other projects, etc. 

 

In Tcl unset removes the value of a variable.  

 

So what is your error from? I have no idea. : ) 

But hopefully that an help debug. Look in the .qip files for an unset. Does the design compile normally?
0 Kudos
Reply