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15553 Discussions

Test kernel that uses IO channel reads from Global Memory more than expected

FSamb
Novice
1,138 Views

What kernel does is just read from Global Memory, then write the same data to write IOchannel. Since reads from GM always has extra reads, it affects the behavior of the write to IO channel.

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10 Replies
FSamb
Novice
276 Views

Forgot to ask the question. Do you have any known issue with implementing IO channel? The kernel seems to do some prefetching of 4 extra bursts of data. Each burst count is 16. Data width is 512b. Total of 4KB extra read.

Nooraini_Y_Intel
Employee
276 Views

Hi,

 

Currently I am reviewing the forum for any open questions and found this thread. I apologize that no one seems to answer this question that you posted. Since it has been a while you posted this question, I'm wondering if you have found the answer? If not, please let me know, I will try to assign someone to assist you. Thank you.

 

Regards,

Nooraini

FSamb
Novice
276 Views
Hi, Thanks for the reply. No, I still haven't found the source of the problem. Would really appreciate some help. Federico
Nooraini_Y_Intel
Employee
276 Views

Hi FSamb,

 

Thank yo for the response. I'm checking here to find someone that may able to assist you on this thread.

 

Regards,

Nooraini

 

FSamb
Novice
276 Views
Thanks, Nooraini. BTW, the same kernel works ok when data to read from GM is big (more than 64KB). Problem happens only if data size is 32KB or less. Federico
Nooraini_Y_Intel
Employee
276 Views

Hi FSamb,

 

Perhaps, can you provide more details on what you are trying to do here? What tools are you using to perform the kernel test to read from the IO channel? Please provide some steps or screen shots. Then it would be easier for us to identify whom can help on this thread as long within FPGA product and tools.

 

Regards,

Nooraini

MelvinSwee_T_Intel
276 Views

hi Federico,

 

Is the kernel referring to OpenCL or SoC?

FSamb
Novice
276 Views
It is an OpenCL kernel for Intel FPGA. Below is an example of the test kernel. This is just a loopback test kernel. Host writes data to GM of FPGA1. ioch_out_kernel reads the data from GM, then writes the same data to ioch_out channel ioch_in_kernel reads the data from ioch_in channel, then writes the same data to GM Host then reads the data from GM of FPGA2. Host should read the same data it writes to GM of FPGA1. For big data transfer (size>=2048, which means 64KB), the test kernel below works ok. If size =< 1024 (32KB or less), the test kernel below doesn't work ok.
MuhammadAr_U_Intel
276 Views

Hi @FSamb​ 

 

What is the version of OpenCL compiler are you using ?

 

Thanks,

Arslan

FSamb
Novice
276 Views
Hi, Arslan. Thanks for replying. Fortunately, the problem is already fixed. IO channel working now. It could be that the strange behavior that I was observing was due to my mistake in the reset that I used for my fifo. Can't explain how they are related. IO channel is a bit hard to debug as it involves multiple FPGAs. Anyway, thanks again for the help. Sorry for the trouble. On Thu, Nov 8, 2018, 8:04 AM Intel Forums <supportreplies@intel.com wrote:
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