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The error in modelsim " Types do not match between component and entity for port "a". Again, I think the testbench is correct. Thanks

NMuth3
Beginner
223 Views

library ieee;                -- line 1

use ieee.std_logic_1164.all;         -- line 2

                       -- line 3

entity find_errors is port(           -- line 4

  a: in std_logic_vector(0 to 3);          -- line 5

  b: out std_logic_vector(3 downto 0);     -- line 6

  c: in std_logic_vector(5 downto 0));      -- line 7

end find_errors;               -- line 8

                       -- line 9

architecture not_good of find_errors is     -- line 10

 begin                   -- line 11

 my_label: process(a)             -- line 12

  begin                  -- line 13

  if c <= x"F" then             -- line 14

   b <= a;                -- line 15

  else                   -- line 16

   b <= "0101";              -- line 17

  end if;                  -- line 18

 end process;                -- line 19

end not_good;                 -- line 20

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1 Reply
RichardTanSY_Intel
187 Views

Could you help to share your quartus project so I can look into it, including the testbench?

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