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The increment operation (++) will cause an error.

wenna
Beginner
555 Views

 

Consider the following code. Using the i++ operation on line 17 causes an error.

 

module test1 (
    input wire clk,          
    input wire reset,        
    output reg [7:0] y       
);

    reg [7:0] data [0:3];    
    integer i;               

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            for (i = 0; i <= 3; i = i+1) begin
                data[i] <= 8'h00; 
            end
            y <= 8'h00;
        end else begin
            for (i = 0; i <= 3; i = i++) begin  
                data[i] <= i * 8'h11;
            end
            y <= data[0] + data[1]; 
        end
    end
endmodule

 

 

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5 Replies
_AK6DN_
Valued Contributor II
541 Views

That is an error. You are writing Verilog, not C. Prefix and postfix ++ and -- are NOT valid operators in Verilog.

And in any event the operation i = i++ is nonsensical. Think about it.

I think you meant to write i = i+1 as you did in line 12.

i++ or ++i would also be logically correct, giving the same result as i=i+1 but as I said earlier they are NOT valid Verilog language syntax.

FvM
Honored Contributor I
485 Views

Unary incre- and decrement operators are supported in system verilog, but make no sense on assignment RHS.

We don't know if SV syntax has been enabled.

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Kenny_Tan
Moderator
420 Views

We have quite a lot of loop example in the Quartus tools itself.


What you will need to do is open up a blank verilog files, right click and insert template. You will see the loop example that you want to do create.


Do let us know if you have further question? If no, we shall close this thread.


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Kenny_Tan
Moderator
367 Views

Not sure if you have further question on this? If no, we shall close this thread.


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Kenny_Tan
Moderator
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