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Consider the following code. Using the i++ operation on line 17 causes an error.
module test1 (
input wire clk,
input wire reset,
output reg [7:0] y
);
reg [7:0] data [0:3];
integer i;
always @(posedge clk or posedge reset) begin
if (reset) begin
for (i = 0; i <= 3; i = i+1) begin
data[i] <= 8'h00;
end
y <= 8'h00;
end else begin
for (i = 0; i <= 3; i = i++) begin
data[i] <= i * 8'h11;
end
y <= data[0] + data[1];
end
end
endmodule
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That is an error. You are writing Verilog, not C. Prefix and postfix ++ and -- are NOT valid operators in Verilog.
And in any event the operation i = i++ is nonsensical. Think about it.
I think you meant to write i = i+1 as you did in line 12.
i++ or ++i would also be logically correct, giving the same result as i=i+1 but as I said earlier they are NOT valid Verilog language syntax.
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Unary incre- and decrement operators are supported in system verilog, but make no sense on assignment RHS.
We don't know if SV syntax has been enabled.
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We have quite a lot of loop example in the Quartus tools itself.
What you will need to do is open up a blank verilog files, right click and insert template. You will see the loop example that you want to do create.
Do let us know if you have further question? If no, we shall close this thread.
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Not sure if you have further question on this? If no, we shall close this thread.
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As we do not receive any response from you on the previous reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
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