TimeQuest Analyzer. False unconstrained clock?

[SrLam9]

Hi,

In the timing analysis of my design, I have one unconstrained clock: csr_control_data_reg[0] which is the control register for the serial flash controller II IP core. The CSR is connected to the HPS using the lightweight bridge. Is there a way to ignore this path as a clock?

I tried running remove_clock -name { csr_control_data_reg[0] } but it returns "Ignored remove_clock: Argument -name with value csr_control_data_reg[0] could not match any element of the following types: ( clk )"

Can a false unconstrained clock cause a system to fail timing or cause timing-related symptoms? I am writing the EPCQL using the Serial Flash Controller II but when I erase, my system becomes unresponsive. A power cycle does not recover and I need to re-program the EPCQ or load a SOF

Thank you!

[KhaiChein_Y_Intel]

Hi,

May I know the full path name for csr_control_data_reg [0]?

Thanks

[a_x_h_75]

I don't think the syntax of your remove_clock is correct. "-name" refers to a name that you have given to something in a timing constraints file, not the name of a signal.

Refer to the Tiemquest reference manual.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_sdctmq.pdf

You may well have to create_clock (using the -name parameter) to tell Timequest to expect a clock and then to remove it - as per the example offered in the reference manual (page 2-54).

Failing that then a set_false_path may be the way to go.

Cheers,

Alex

[SrLam9]

Hi KYeoh,

The full path is :

hps:u0|hps_altera_epcq_controller2_180_y5ic34y:epcq_controller2_0|hps_altera_asmi_parallel2_180_2o4p2ly:asmi2_inst_epcq_ctrl|hps_altera_asmi2_csr_controller_180_rio6xka:csr_controller|csr_control_data_reg[0]

that is the path/signal it shows me in the TimeQuest Clock Status Summary window.

Hi a_x_h_75,

I definitely need to familiarize myself more with TimeQuest.

Thank you

[sstrell]

You can't false path something the tool considers a clock path. False path only prevents data path analysis on the path, not clock path analysis. If this path is indeed going to the clock input of the IP, you need a create_clock (or more likely create_generated_clock) constraint.

What I don't understand is why a CSR path is being considered a clock path in your design. I haven't used that IP, so maybe you need to check the IP's user guide to figure out what's going on here.

[KhaiChein_Y_Intel]

What is the Device OPN you are using?

[SrLam9]

Hi sstrell,

Thank you for the clarification. I will look into the user guide again. Yea I also do not understand why the CSR path is considered a clock path.

Hi KYeoh,

I am not sure what a Device OPN is, but I am using an Arria 10 with EPCQL512

Thank you

[KhaiChein_Y_Intel]

Hi,

What is the full name of this IP?

Thanks.

[SrLam9]

Hi,

Serial Flash Controller II Intel FPGA IP.

I have it named epcq_controller2_0 in my platform designer project.

Thank you

[KhaiChein_Y_Intel]

Hi SrLam9,

Upon checking, csr_control_data_reg [0] in Serial Flash Controller II Intel FPGA IP is not a clock. It can be safely ignored.

Thanks.