TimeQuest Clock Assignments

[Altera_Forum]

Hi All, 

 I'm closing the timing on a design using the EP3C5 series Cyclone III and there is a discrepancy on some of my signals as to which clock they are being assigned. I have three main clocks; the primary system clock, a USB clock for serial communication, and a read clock coming off a microprocessor for taking the output data from the FPGA. In my TQ reports though, several signals are reported as being clocked by the wrong source (ie - the signal should be controlled by the system clock but is being reported as being clocked by the USB clock). Is there a tcl command I need to be using to make sure my signals are clocked by the right source? If TQ is reporting my clock assignments incorrectly, will I see improper behavior of my design?

[Altera_Forum]

I haven't seen that happen before. If you run "report_timing -setup -npaths 20 -detail full_path -panel_name test" and maybe add -from or -to to get the paths you're talking about, the detailed report should show how the register traces back to the clock driving it. It has to be a path that physically exists in the design. So either it will trace back to something you didn't expect or the clock constraint was applied to the wrong node. (At least those are my guesses).