Timing Analysis False Paths Question

[BTayl147]

I just had a quick question about False Paths maybe someone could answer?  When I generate a report for unconstrained paths and view the  "Unconstrained Input Port Paths" I have a report like the picture below.

 

You can see the paths are not associated with a clock.  Is this where you would use False Paths for proper constraining?  If not could you point me in the proper direction?

Thanks in advance for the help!

 Brandon

[sstrell · Accepted solution]

Yes.  If these are asynchronous inputs (DIP switches for sure looking at the top of your report), you would false path them:

set_false_path -from [get_ports DIP_DATA*]

for example.

#iwork4intel

[BTayl147]

sstrell,

Thank-you for your help!  That's what I will do.

Have a good day!

Brandon