my current Design has a TNS of 0.175ns which i cant get rid of.
i tried to constrain all of my paths with some reasonable values:
But no matter what i enter for the four "user" clocks the TNS on clk stays at 0.175ns (since im just validating a concept i can adjust the clock speeds to my liking but i try of course to use realistic values.) Since the altera_reversed_tck is auto generated i did not touch it, but with the other i tried a variety of Values with absolutely no effect on the TNS.
The failling Path is this one:
What am i missing here?
Thanks in Advance
Without seeing the complete timing report for that path (full path detail level), you have a relatively large clock skew there. You're transferring data between two clock domains (spi_clk to clock), so perhaps you need multicycle timing constraints or to add registers. Is this within an IP or just your own logic? More detail about the failing path and your design needed.
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