Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Timing Constraints and TNS

Matthias0
Beginner
236 Views

Hi there,

my current Design has a TNS of 0.175ns which i cant get rid of.

Screenshot from 2022-05-19 08-33-44.png

i tried to constrain all of my paths with some reasonable values:

Screenshot from 2022-05-19 08-42-19.png

 But no matter what i enter for the four "user" clocks the TNS on clk stays at 0.175ns (since im just validating a concept i can adjust the clock speeds to my liking but i try of course to use realistic values.) Since the altera_reversed_tck is auto generated i did not touch it, but with the other i tried a variety of Values with absolutely no effect on the TNS.

The failling Path is this one:

Screenshot from 2022-05-19 08-43-18.png

What am i missing here?

Thanks in Advance

Matthias

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3 Replies
sstrell
Honored Contributor III
213 Views

Without seeing the complete timing report for that path (full path detail level), you have a relatively large clock skew there.  You're transferring data between two clock domains (spi_clk to clock), so perhaps you need multicycle timing constraints or to add registers.  Is this within an IP or just your own logic?  More detail about the failing path and your design needed.

Nurina
Employee
192 Views

Hi,


Does above reply help?


Nurina
Employee
164 Views

Hi,


We did not receive any response to the previous question/reply/answer provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.


Regards,

Nurina


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