Timing-Driven Synthesis is skipped because it could not initialize the timing netlist

[OlaG]

Using DCFIFO IP with standard settings causes timing-driven synthesis to be skipped and seems to create some timing issues in the design (optimizing of cells that should not me optimized). Warning message:

Warning (330000): Timing-Driven Synthesis is skipped because it could not initialize the timing netlist

I have found the cause of the warning, instantiating a FIFO (v22.1) with the default option checked. "Generate SDC files and disable embedded constraint". Disabling that option seems to restore the execution of timing-driven synthesis. I would think this is a bug, since this option is checked by default and even recommended by Intel to reach timing for high-freq DCFIFO (https://www.intel.com/content/www/us/en/docs/programmable/683522/18-0/dcfifo-timing-constraint-setting.html).

I'm worried that unchecking this option also introduces incorrect false paths as mentioned here: https://www.intel.com/content/www/us/en/support/programmable/articles/000084486.html

Am I right to worry? Is there anything else I should know?

Quartus Prime version: Version 22.1std.2 Build 922 07/20/2023 SC Standard Edition

FPGA: Arria 10

IP settings: attached (option that causes issue unchecked)

[ShengN_Intel]

Hi,

I had reported this issue to internal team. I'll come back to you once there's any further feedback from internal team. Please allow some time for investigating.

Thanks,

Best Regards,

Sheng

[ShengN_Intel]

Hi,

Based on internal team, you may ignore the warning as it is not going to cause any functional issue and not affecting much.

Let me know if it causes IP timing not met or any performance degradation issue.

Thanks,

Sheng

[OlaG]

Dear Sheng,

Thank you for your quick feedback! I am a little surprised since this message seems to indicate that optimization could merge registers with incompatible timing, according to

"Timing-Driven Synthesis prevents registers with incompatible timing constraints from merging for any Optimization Technique setting." in https://www.intel.com/content/www/us/en/docs/programmable/683283/18-1/enabling-timing-driven-synthesis.html

What does the internal team recommend, to keep the option "Generate SDC files and disable embedded constraint" checked or not? Are there any detrimental effects of keeping it unchecked?

[ShengN_Intel]

Hi,

It's recommended to check the option "Generate SDC files and disable embedded constraint". If not, keeping it unchecked will cause FIFO hardware failure for high frequency design.

Based on internal feedback, it's safe to ignore the warning as it wouldn't affect much on FIFO functional and timing.

Thanks,

Best Regards,

Sheng