Timing Violations in JTAG Signals

[FabianL]

Hello,

I have a Arria10 FPGA design using Platform Desginer which includes a Avalon to JTAG Brdige.

I have added a jtag.sdc file to the project based on this guideline: JTAG Signals

and set all the "--customize here--" sections according to my design (see attached sdc file).

However the Timing Analyzer gives me several setup violations on JTAG signals:

-18.207	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_8	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.582	4.240	Slow 950mV 100C Model
-18.206	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_9	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.582	4.239	Slow 950mV 100C Model
-18.157	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_7	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.582	4.190	Slow 950mV 100C Model
-18.142	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_10	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.582	4.175	Slow 950mV 100C Model
-18.123	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_11	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.582	4.156	Slow 950mV 100C Model
-18.120	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_6	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.582	4.153	Slow 950mV 100C Model
-17.207	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_1	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.125	3.697	Slow 950mV 0C Model
-17.136	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_3	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.125	3.626	Slow 950mV 0C Model
-17.069	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_2	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.125	3.559	Slow 950mV 0C Model
-17.064	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_4	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.125	3.554	Slow 950mV 0C Model
-16.972	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-2.125	3.462	Slow 950mV 0C Model
-16.075	auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|atom_inst|atom~jtag_reg__nff	altera_reserved_tdo	altera_reserved_tck (INVERTED)	altera_reserved_tck (INVERTED)	33.333	-0.450	4.240	Slow 950mV 0C Model

The listed registers look similar but not identical to the security reg listing in the jtag.sdc line 86-89 which are to be ignored.

So I'm not sure if  these errors are actual errors caused, e.g. by a too high JTAG clock rate, or if these registers are just missing a respective false path due to encrypted core.

The Timing Analyzer does list the falling paths as encrypted:

Please advise how to deal with these JTAG signal in timing analysis.

Thanks

Fabian

[sstrell]

You say jtag.sdc was added to the project, but is it listed in the Timing Analyzer settings in the Settings dialog box?  Very common issue to forget to to add that there.

[Kenny_Tan]

Can you attached your design.qar file to take a look?

[FabianL]

The sdc file is active in the project and  also in the timing Analyzer settings. 

I am sorry, I cannot share my complete project, as it contains Intellectual Property of the company.

The failing paths are explicitly not covered by the .sdc constraint from the Intel Manual:

# Cut a few timing paths that are not related to JTAG logic in
# the FPGA core, such as security mode.
set_false_path -from [get_ports {altera_reserved_tdi}] -to [get_ports {altera_reserved_tdo}]
if { [get_collection_size [get_registers -nowarn *~jtag_reg]] > 0 } {
set_false_path -from [get_registers *~jtag_reg] -to [get_ports {altera_reserved_tdo}]
}

The violations are about the tdo_reg

-18.207 auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|jtagpins|int_tdo_reg~LRTM_8 altera_reserved_tdo altera_reserved_tck (INVERTED) altera_reserved_tck (INVERTED) 33.333 -2.582 4.240 Slow 950mV 100C Model

The Question is, is this intentional? and how to debug timing issues within an encrypted core?

Or are the tdo_reg constraints missing in the sdc file?

Thanks

Fabian

[Kenny_Tan]

1) Can you double check if you have missing constrain by following the below:

https://www.intel.com/content/www/us/en/support/programmable/articles/000092769.html

2) Do you have signal tap added to your design? If yes, can you temporally remove the signal tap and see if there are still timing violation?

[FabianL]

1) I did the check with the mentioned sdc template and it matches completely the design .sdc file, except for an assignment which is only valid for Stratix10. Since I'm using Aria 10 this won't be applied.

2) I don't have any signal tap in my design. The only thing I use is JTAG to Avalon Master Bridge Intel FPGA IP Version 19.1 which accesses the main Avalon system bus

best regards

Fabian

[Kenny_Tan]

Can you temporally try to remove that IP to see if that is the root cause?

[FabianL]

I just removed the IP and still have the timing errors.

I also managed to create a very simple example project with basically nothing in it. It also shows timing errors related to JTAG TDO Pins, even though it's about different source nodes. Maybe that helps to analyze the problem. 

[Kenny_Tan]

After running several tests on a smaller design, we observed that violations may occur if Signal Tap has been previously enabled. Once enabled, Quartus tends to retain the configuration and automatically adds an additional module named auto_fab_0. The issue appears to be linked to the encrypted Signal Tap IP.

To address this, please ensure that all constraints are properly defined for your board. You may need to customize the constraint settings accordingly. For reference, Intel provides detailed guidance on JTAG constraints here:

JTAG Constraints File – Timing Analyzer Cookbook

If all constraints are correctly applied and aligned with your board configuration, we recommend reducing the operating frequency to 16 MHz as a next step.

https://www.intel.com/content/www/us/en/docs/programmable/683719/current/jtag-timing-constraints-and-waveforms.html

Additionally, I will further investigate whether this issue is related to a potential bug in the current version of Quartus by comparing it with older releases. I’ll follow up with more findings soon. Thanks