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Sajith_K_Intel
Employee
270 Views

Timing driven synthesis option is not found in Quartus 19.4 when Agilex device is selected

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When using Agilex device in Quartus 19.4, There is no option to set Timing driven synthesis (in advanced synthesis settings). Hence I am not sure if SDC file will be considered during synthesis.

 

From Logs, there is no mention about SDC file during synthesis stage. But SDC is loaded only during plan stage. How can i enable SDC file during synthesis?

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KennyT_Intel
Moderator
91 Views

For Agilex, this feature had been drop

View solution in original post

15 Replies
KennyT_Intel
Moderator
91 Views

If you refer to https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#logicops/logicops...

 

This options does not support agilex device.

 

Unlike standard edition, you will have to use SDC files on the fitter plan stage itself.

Sajith_K_Intel
Employee
91 Views

Do you know why it is not there for Agilex? or do we have an alternate option wgen using Agilex?

 

In such a case, how do we make sure synthesis is aware of my timing constraints to optimize the design?

KennyT_Intel
Moderator
91 Views

Timing driven synthesis was enable by default in Pro. You do not need to do any thing unless you want to disable it.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-qpp-compiler...

 

page 11

 

As long as you put your constrain sdc files in assignemtn -> setting -> timing analyzer. it should be sufficient to let Quartus know that you had use your timing constrain.

Sajith_K_Intel
Employee
91 Views

If so, shouldnt there be a mention about SDC in synthesis log? Bit it is not doing.

I think synthesis step then should throw syntax errors from SDC file. Somehow this is not happening.

KennyT_Intel
Moderator
91 Views

Do you have a simple design example for Pro and Std? I will make a comparison here and get back to you.

 

Basically, I do think that synthesis steps should throw syntax error from the SDC since sdc is being taking care of in synthesis when using timing driven synthesis.

Sajith_K_Intel
Employee
91 Views

I can provide a sample design of Pro, not Standard as i do not have it.

As you said, timing driven synthesis is by default ON. then why do yo think synthesis will not consider sdc errors?

 

In the attached example, i do not see any info messages about sdc during synthesis.

KennyT_Intel
Moderator
91 Views

base on your design. I move it to standard of Quartus. And purposely set the incorrect port to your sdc.

 

create_clock -name clk -period 10 [get_ports clockABC]

 

When I run the synthesis on both pro and std. I don't see any sdc error or warning. this is for apple to apple comparison.

 

Sajith_K_Intel
Employee
91 Views

Yes you are right.

This is why I doubt if Timing information is considered or not during synthesis

KennyT_Intel
Moderator
91 Views

Internally, it should. However, they don't check on sdc error. Which means, it will take the sdc that is written incorrectly, either ignore it and implement wrongly on it. Thus, when your synthesis, you might not get accurate timing synthesis.

 

However, in fitter stage, those sdc written will still be catch and user had to modify it there.

Sajith_K_Intel
Employee
91 Views

It does mean, there is no way to make sure synthesis was done really timing driven?

KennyT_Intel
Moderator
91 Views

you can still check in compilation report -> synthesis -> settings -> settings

 

Over there, you should see this option was on.

Sajith_K_Intel
Employee
91 Views

But there is no setting on "timing driven synthesis" for Agilex. This is what i was asking here.

KennyT_Intel
Moderator
91 Views

Let me check with developer, Agilex are new device.

KennyT_Intel
Moderator
92 Views

For Agilex, this feature had been drop

View solution in original post

Sajith_K_Intel
Employee
91 Views

Understood. Thank you

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