When using Agilex device in Quartus 19.4, There is no option to set Timing driven synthesis (in advanced synthesis settings). Hence I am not sure if SDC file will be considered during synthesis.
From Logs, there is no mention about SDC file during synthesis stage. But SDC is loaded only during plan stage. How can i enable SDC file during synthesis?
This options does not support agilex device.
Unlike standard edition, you will have to use SDC files on the fitter plan stage itself.
Do you know why it is not there for Agilex? or do we have an alternate option wgen using Agilex?
In such a case, how do we make sure synthesis is aware of my timing constraints to optimize the design?
Timing driven synthesis was enable by default in Pro. You do not need to do any thing unless you want to disable it.
As long as you put your constrain sdc files in assignemtn -> setting -> timing analyzer. it should be sufficient to let Quartus know that you had use your timing constrain.
If so, shouldnt there be a mention about SDC in synthesis log? Bit it is not doing.
I think synthesis step then should throw syntax errors from SDC file. Somehow this is not happening.
Do you have a simple design example for Pro and Std? I will make a comparison here and get back to you.
Basically, I do think that synthesis steps should throw syntax error from the SDC since sdc is being taking care of in synthesis when using timing driven synthesis.
I can provide a sample design of Pro, not Standard as i do not have it.
As you said, timing driven synthesis is by default ON. then why do yo think synthesis will not consider sdc errors?
In the attached example, i do not see any info messages about sdc during synthesis.
base on your design. I move it to standard of Quartus. And purposely set the incorrect port to your sdc.
create_clock -name clk -period 10 [get_ports clockABC]
When I run the synthesis on both pro and std. I don't see any sdc error or warning. this is for apple to apple comparison.
Internally, it should. However, they don't check on sdc error. Which means, it will take the sdc that is written incorrectly, either ignore it and implement wrongly on it. Thus, when your synthesis, you might not get accurate timing synthesis.
However, in fitter stage, those sdc written will still be catch and user had to modify it there.