Timing issues between D5M camera module and PIOs buttons in NIOSII SBT

[Altera_Forum]

Hello everyone 

I am of course no vice specially in timing the design. Kindly refer to the snapshot of my qsys system. This is in short a video capture system using D5M CMOS camera on DE-4 board. Video capture works pretty fine. The problem I face is in Software side and not in Hardware side. I mean in NIOS eclipse environment with C language, when I press pioButton have no effect i.e. code which is expected to run is not running. But when I press Hardware reset, very quickly after pressing reset the pioButton works fine. And as soon the video capture is started and getting displayed again on screen, the pioButton again goes like dead.  in simple words video capture + display is working like mutually exclusive with piobutton. either of these two may work. once video capture is started piobutton have no effect.  All the connections are very well clear in snapshot. Other details:  DDR2 memory device speed grade is 533.333MHz; in general settings speed grade is 2; Memory clock frequency is 400MHz; PLL reference clock frequency is 50MHz; then you may see afi_clk is connected to all IPs except PIOs which are connected to 10MHz clock derived from pllInternal alt_pll IP.  Avalon MM-Clock crossing bridge master clock is connected to 10Mhz from alt_pll and slave clock with afi_clk of DDR.  my question is: Is there any necessary IP I must use to synchronize the events of PIOs and camera module (inculdes IPs Terasic_Camera, FrameBuffer, and Clocked Video Output)? Or clocks distribution I am providing is wrong?  NOTE: C language code have no problem as I have tested the code running smoothly when after removing the Camera module which means disabling the camera and video capture gives no problem in Software at all.  Thanks a lot in advance. Snapshot is below: https://alteraforum.com/forum/attachment.php?attachmentid=15590&stc=1