Timing requirement not met?

Altera_Forum · ‎02-10-2011

Could anyone tell me what causes this happen to my code?

After compilation, I got clk Slack -4.076 and End Point TNS -73.368;

All the stuff under the minimum Pulse width:'clk' report is in red...also the same thing for setup summary.

Thanks in advance...


module memory(clk,mem_oe,mem_rw,addr,mem_data); 
input clk,mem_oe,mem_rw; 
//mem_oe=1 for memory output enable, mem_oe=0 output=ZZZZ...
//mem_rw=0 for read, mem_rw=1 for write
input addr; 
inout mem_data;
wire mem_data;
reg ram; 
reg data_out;
//integer i;
assign mem_data = (!mem_rw&&mem_oe) ? data_out : 18'bz;
 
        always@(posedge clk)
        begin 
           if(!mem_rw) // read from the memory
             begin
                  data_out<=ram; 
             end
            
            else          // write to the memory
             begin
                  ram <= mem_data;
             end
        end
endmodule

Altera_Forum · ‎02-10-2011

by the way, in the simulation, this circuits does work.

And im quite confused about this kind of timing requirements warnings.

Altera_Forum · ‎02-10-2011

How long are mem_rw and mem_oe pulses?

If they are asserted more than one clock period you simply need to define a multicycle path.

Altera_Forum · ‎02-10-2011

This does not look like a problem with the code.

It looks like you're imposing a too high clock frequency to your design.

Which is the clock frequency that you impose to your design?

Do things work if you reduce the clock frequency to very small value?

Altera_Forum · ‎02-10-2011

--- Quote Start ---

This does not look like a problem with the code.

It looks like you're imposing a too high clock frequency to your design.

Which is the clock frequency that you impose to your design?

Do things work if you reduce the clock frequency to very small value?

--- Quote End ---

Hi,

I don't know if i did impose any clock frequency to my design. Is there like a default

clock frequency that's imposed when compilation?

Altera_Forum · ‎02-11-2011

After the compile, run TimeQuest. Double click "Report Clocks" and make sure your clock frequency is what you specified it to be. You can also run "Report Unconstrained Paths" and if your clock is not constrained, it will show up there. I am assuming you constrained your clock. If you did not, create a .sdc file to constrain the clock.

Altera_Forum · ‎02-11-2011

--- Quote Start ---

After the compile, run TimeQuest. Double click "Report Clocks" and make sure your clock frequency is what you specified it to be. You can also run "Report Unconstrained Paths" and if your clock is not constrained, it will show up there. I am assuming you constrained your clock. If you did not, create a .sdc file to constrain the clock.

--- Quote End ---

Hi,

I assume that you run the simulation with your RTL code. This simulation did not take into account any delay which you will have later on when the design is implemented in the FPGA. What you test with this simulation is the function of your design. But in the FPGA you will delays between your registers ( routing delay and cell delay). These delays limits

the maximum frequency which you can use running your design. You always constraint your clocks, because Quartus needs this for opitimizing your design in the right way.

Kind regards

GPK

Altera_Forum · ‎02-11-2011

Hi,

if you do not create any clock, Timequest automatically creates a clock with a frequency of 1GHz and analyzes timings with this clock.

Altera_Forum · ‎02-11-2011

Got it. Thanks for you guys.