Tri0 and Pulldown synthesizable in CPLDs (MAX V, MAX II, MAX7000)

[CHess4]

Hello!

I am implementing a simple bus hub design. I would like to use pulldowns for some of my inout ports. Quartus lets me compile Tri0, but gives an error when I use pulldown on the same nets - "will not synthesize". Now I am reading elsewhere that tri0 won't synthesize either.

Is there a way to implement input pull downs on Max V, Max II or Max 7000 devices?

Or where should I ask such kind of questions?

Thank you

[Rahul_S_Intel1]

Hi ,

There is an option for the unused pin to make it as pull up, the options available is on the Device and Pin options >> Unused pins

[Rahul_S_Intel1]

Hi ,

 Kindly let me know if you need further assistance.