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Hi All,
I'm using a Max 10 FPGA. I'm having trouble instantiating a d flip flop initially set to '1'. From the altera.altera_primitives_components.all I am instantiating the following: component dff port ( D : in std_logic; -- Data Input CLK : in std_logic; -- 100 MHz clock CLRN : in std_logic; -- Clear Input PRN : in std_logic; -- Preset Input Q : out std_logic -- Output Data ); end component; But there is no generic that let's me hardcore a '1' there? I want to shift in 0's when the power is recycled (by tying the pin to ground) and so I need the initial value of the register to power up to '1'. Thank you for your help. Bryan Kerr Electronics EngineerLink Copied
2 Replies
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Why are you using the primitives? why not infer the register, because then you can apply the initial value yourself:
signal q : std_logic := '1'; -- initial value
....
process(clk)
begin
if clrn = '0' then
q <= '0';
elsif prn = '0' then
q <= '1'
elsif rising_edge(clk) then
q <= d;
end if;
end process;
If a register has async clear, it often uses this as the power on value if none is specified. If you have to use the primitives, I think you can assign the power on value in the project assignments. You will need to compile the project to get the register path from the node finder.
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Consider that simultaneous asynchronous reset and preset isn't supported by MAX10 logic elements. It has to be emulated by a combination of DFF and combinational logic, including latches.
The dffeas primitive component and the ff wysiwyg component have a power_up generic, by the way.
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