Trouble simulating altiobuf in ModelSim

[Altera_Forum]

I'm having issues simulating the altiobuf_[in|out] megafunctions using Modelsim. I'm directly instantiating them in the code instead of using the megafunction wizard (the files the wizard generates are not portable across FPGA families, nor are they parameterized), and everything compiles and works fine in the real FPGA. However, when trying to simulate in Modelsim, it can't find the megafunctions: 

 ** Error: (vsim-3033) C:/blahblahblah/dac_driver/rtl/main/dac_driver_fpga.v(171): Instantiation of 'altiobuf_in' failed. The design unit was not found.# Region: /full_dac_driver_tb/driver# Searched libraries:# C:\altera\91\modelsim_ase\altera\verilog\altera# C:\altera\91\modelsim_ase\altera\verilog\220model# C:\altera\91\modelsim_ase\altera\verilog\sgate# C:\altera\91\modelsim_ase\altera\verilog\altera_mf# C:\altera\91\modelsim_ase\altera\verilog\stratixiii# C:\blahblahblah\dac_driver\project\altera\simulation\modelsim\rtl_work# C:blahblahblah\dac_driver\project\altera\simulation\modelsim\rtl_work# C:\blahblahblah\dac_driver\project\altera\simulation\modelsim\rtl_work   The user guide for the altiobuf megafunction mentions that the simulation must run using the altera_mf library, but that library doesn't seem to contain the correct module (and the raw verilog file doesn't seem to have it either).  Am I missing something, or is Altera missing something from their simulator files? This is rather frustrating, because I know the direct instantiation works in silicon (I can see the data when I drive it with a known good source), but I need to be able to simulate it to make sure I'm interleaving properly for my LVDS serializers.

[Altera_Forum]

Just as an update, if I look at what the megafunction wizard generates, it's just a load of StratixIII I/O atoms in a file. If I look at the TDF autogenerated by the direct instantiation when it's compiled, I get what looks like an AHDL file which eventually generates a StratixIII atom (in this compilation), which is what I want. I don't have issues with any of my other directly instantiated elements (dcfifo, etc) which do the same sort of thing.

[Altera_Forum]

the altera_mf in quartus/eda/sim_lib does not have an altiobuf, but the one in quartus/eda/synthesis does. try compiling that as a library and replacing the ModelSim-AE provided altera_mf library.

[BrianHG]

I'm using QuartusPrime 20.1 and I have the same problem.  I need to simulate a design using 'altiobuf_bidir' for my differential DQS IO signal transceiver.  I looked in the quartus/eda/ and found the sim_lib, but, I did not find the quartus/eda/synthesis folder.  How can I get my design to simulate?

Also, if I were to make my systemverilog source public, how do I make it so that others can effortlessly simulate my source code?