Trying to assign I/O pins for LVDS on Cyclone 10 LP

[Andy-1]

I wondered if anyone could point me in the right direction on how to implement LVDS using the Quartus Prime Lite software. I have read documentation from both Altera and Intel on how to setup LVDS and I have used the ALTLVDS_TX and ALTLVDS_RX MegaWizards. However, I am unable to link the inputs and outputs to the physical I/O of the Cyclone CL 016. I would very much appreciate some help in this area.

Thanks

[FvM]

Hi,
LVDS IOs are simply set up by assigning LVDS IO standard to the (single ended) in- and output ports of LVDS IP or serdes implemented in HDL code. You have to select a pin that is specified as positive pin of a dedicated LVDS pair, the negative pin is then assigned automatically. Pin planner tool shows suitable pins or can select them automatically. The respective pin must use 2.5 V VCCIO.

Regards
Frank

[Andy-1]

Hi Frank, thank you so much for taking the time to respond. I have to admit that I am still slightly confused. To give some context I am using an LVDS IC that requires a driver input, I would like to connect this pin to an output port on the Cyclone, which in my case is something like b_MKR_D[5]. In my Pin Planner I can only set the I/O standard for the available I/O pins to 2.5v I don't have 2.5V V VCCIO for these pins, therefore how can I associate the TX_out from the ALTLVDS output with pin b_MKR_D[5], so that I can use the LVDS IC. Furthermore, if you know of any tutorial or relevant documentation please let me know. Thanks.

[FvM]

Hi,
to implement LVDS I/O according to Cyclone 10 specifications, VCCIO of 2.5 V is required for the respective banks.

I don't know if the intended pin is dedicated LVDS I/O. For slower LVDS speed (a few 100 MBPS), it's possible to use single ended I/O as emulated LVDS with resistor network to set the output level, also for 3.3V VCCIO. But LVDS RX is only available on dedicated LVDS pin pairs.

Regards
Frank

[AqidAyman_Intel]

You can only set the I/O standard for the available I/O pins to 2.5 because LVDS I/O standard in Cyclone 10LP is using 2.5V VCCIO. You can refer to the datasheet from below link:

https://www.intel.com/content/www/us/en/docs/programmable/683251/current/differential-i-o-standard-specifications.html

[Andy-1]

Thank you for taking the time to reply to my question, I have a much better understanding now. Thanks

[AqidAyman_Intel]

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