Unable to generate example design Serial Lite 3 streaming Intel Arria 10 FPGA IP using Quartus tools

[NMani1]

Greetings,

I am using Quartus 18.1 to generate the example design for Serial Lite 3 streaming Intel Arria 10 FPGA IP after configuring the parameters and the preset. The process of generating the example design in Quartus tools is taking more than 30 mins. I suspect there is something wrong or maybe I am missing some things.

I am trying to generate the design on Debian and I am using Quartus 18.1. I have also tested the generation on Windows and it sadly didn't generate.

I will happy to know if there are any pointers on how to solve this issue or to raise a service request.

Please find attached a screenshot of the process for your reference.

[Nathan_R_Intel]

Hie,

I have checked with Quartus Prime Pro 18.1. The Example design can be generated if you follow the following steps:

1. Select Preset "Standard Clocking Mode 6 x12.5G" and click "Apply". The Preset is located in window at bottom right of the Serial Lite III Streaming Intel Arria 10 FPGA IP.

2. Change Direction from "Duplex" to "Source".

You will not observe only 2 warning instead of 8 warnings as shown in your attached snapshot.

Regards,

Nathan

[NMani1]

Hello Nathan,

Thanks for your reply and offering your suggestion. I have access to Quartus Prime 18.1 standard edition only. And I followed your steps on the standard edition and it doesn't work. Could you please confirm if the core generates only on Quartus Prime Pro 18.1 and not on the Quartus Prime 18.1 standard edition.

Thanks,

Neels

[Nathan_R_Intel]

​Hies Neels,

Yes currently the Quartus Prime 18.1 Standard is showing some issues generating the example design. Hence, a ticket has been submitted to the internal engineering teams to fix this issue in our future Quartus updates. My apologies but at this point, I don't have a workaround for this with Quartus Prime 18.1 Standard.

Regards,

Nathan

[NMani1]

Hi Nathan,

Thanks for your reply.

It seems, we can temporarily fix the issue by installing Stratix V devices. I initially had only arria 10 devices. There seems to be some dependency on having Stratix V devices to generate the Serial lite example for arrria 10 devices.

But still, I am able to generate the example design (hw+sw) only for the preset configurations. For custom configurations, only simulation files are generated. I have opened a case in IPS, I am waiting for it to be sorted.

Thanks,

Neels

[Nathan_R_Intel]

​Hie Neels,

Good news you identified a temporary workaround. I will be adding this issue to our knowledge database and an update accordingly on when the fix will be incorporated.

Regards,

Nathan