Unable to synthesis design if defines are included in seperate file

[Abhishek_C_Intel]

I am synthesizing my design in quartus prime. The FPGA used in our design is stratix 10. I am synthesis a synopsys designware IP. The IP has separate files for defines and these defines were saved as .v files. I tried synthesizing the design but quartus is generating critical warning and errors as I could not locate these defines in Verilog files. In order to synthesis I tried various but I am still unable to synthesis my design below are the options which I tried

set_global_assignment -name VERILOG_FILE      "../../../spi_master_DW_apb_ssi_cc_constants”

set_global_assignment -name VERILOG_INCLUDE_FILE      "../../../spi_master_DW_apb_ssi_cc_constants”

[AnandRaj_S_Intel]

Hi,

You can refer simple example below.

----------------------------------------------

and_op.v

-----------------------------------------------

module and_op (a, b, c);

`include "macro.v"

output a;

input b, c;

`ifdef behavioral

wire a = b & c;

`else

or a1 (a,b,c);

`endif

endmodule

--------------------------------------------------

macro.v

--------------------------------------------------

`define behavioral

--------------------------------------------------

Refer below link for more information

Intel Quartus Prime Integrated Synthesis of https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/qts/qts-qps-5v1.pdf

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd07231998_9862.html

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

[Abhishek_C_Intel]

Hi, Thank you for your response. My question is I am having two files which contains `define and the other files which are using it. In my file list I have maintained the order of files so that files containing `defines are read first. Still quartus is generating an error. I am not facing this issue with any other synthesis tool like Xilinx vivado or synplifypro etc. I checked the switches/options for set_global_assignment and found that we can use VERILOG_INCLUDE_FILE switch/option. Yet the tool is generating the error. I think this issue is only related to quartus. Is there a way to avoid manually editing the files and use options/switches available with set_gobal_assignment. Thanks & Regards Abhishek

[SAR]

Hi,

I just synthesized a design with an include file with extension .inc and it works fine. You can use the following line in the projects QSF file:

set_global_assignment -name INCLUDE_FILE <path_to_file>

or

set_global_assignment –name VERILOG_FILE <path_to_file> (if the file has extension .v)

and not

set_global_assignment –name VERILOG_INCLUDE_FILE < >

The path has to be absolute (full path) and not relative (../../../..) . Save the QSF file and then rerun the synthesis. The user can also try placing the include file in the same folder as the rest of the RTL source files.

If you are doing so via the Quartus GUI, then add the include files into the project via Project -> Add / Remove Source files option. This is equivalent to the set_global_assignment –name INCLUDE_FILE statement and will make sure the include files are taken into consideration for synthesis and rest of the flow.

If the include file has the .v extension, then use the

set_global_assignment –name VERILOG_FILE <> statement in the QSF file ad include it as a regular Verilog file.

[SAR]

Hi,

You can take a look at the opencores design that I used for the above two methods. The original design has the include file with extension .inc and I’ve modified it with extension .v and have quartus compile the design.