Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Unable to use design security feature in Quartus II

Altera_Forum
Honored Contributor II
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I am trying to generate key programing file for my design as described in this app note: http://www.altera.com/literature/an/an341.pdf 

 

However when I do step i on page 13, to open up sof file properties, the only option available to me is "compression". There are no bitstream encryption options available.  

I am trying to convert a sof that for a stratix II device using Quartus II 8.1 with a full license. 

 

Has anyone come across this issue or know how to fix it?
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Altera_Forum
Honored Contributor II
796 Views

You need to file an SR with Altera to get two items. 

 

An ini file to be able to program the the actual key into the part. 

 

A license feature to allw you to generate the encrypted file. 

 

(Altera has to keep track of who has the potential to encrypt parts should the government wish to know who is keying devices in the future - they don't care now, but could change their mind some day.) 

 

File the SR.
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Altera_Forum
Honored Contributor II
796 Views

I have finally come back to attempting to configure the flash memory on the stratix II dsp board with an encrypted bit stream. 

 

I believe the bitstream is being encrypted ok and also downloaded to the flash ok. However, when I reset the board it fails to configure the FPGA. 

I have configured the FPGA with the generated key file .ekp using the ethernet blaster. 

 

I haven't done anything with an ini file. I am not sure what this does or why it is required for the encryption programming. 

 

Would you be able to explain more about this, Avatar, or anyone else who has come across this before?
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Altera_Forum
Honored Contributor II
796 Views

You should work this issue via an SR with the factory.

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Altera_Forum
Honored Contributor II
796 Views

I am facing the same question. the key(.ekp) has been download to StratixIII(if I download it again, the QuartusII will popup an error and tell me the key cannot be download again) by ethernetblaster. the encrypted .pof has been programmed to an EPCs64. But when I power the board, it cannot config the FPGA. 

 

BTW: the unencrypted pof file in the EPCs64 can config FPGA successfully. 

 

Would you be able to explain more about this, Avatar, or anyone else who has come across this before? 

 

 

 

--- Quote Start ---  

I have finally come back to attempting to configure the flash memory on the stratix II dsp board with an encrypted bit stream. 

 

I believe the bitstream is being encrypted ok and also downloaded to the flash ok. However, when I reset the board it fails to configure the FPGA. 

I have configured the FPGA with the generated key file .ekp using the ethernet blaster. 

 

I haven't done anything with an ini file. I am not sure what this does or why it is required for the encryption programming. 

 

Would you be able to explain more about this, Avatar, or anyone else who has come across this before? 

--- Quote End ---  

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Altera_Forum
Honored Contributor II
796 Views

I had problems to use design security with non-volatile key and Arria II Gx.  

It doesn't works with compression feature. It only works with bitstream with normal size. Is it a bug?
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