Unable to write to on-chip memory using Avalon Write Master.

[Ashish_Pradhan]

Hello,

  I am trying to write to an on-chip memory using Avalon Write Master Intel FPGA IP ( dma_write_master version 19.2.0, a sub-core of mSGDMA  ) configured as stream to memory-map.

- I am exporting all the channels (Command_sink, Data_sink, Data_Write_Master, Response_Source) and driving them through a test bench.

- I am configuring the 256-bit command_sink_data ( As per the user guide of mSGDMA "Extended Descriptor Format", Table-314 ). 

In simulation waveform, I can see appropriate transitions and correct values on master_writedata, master_byteenable, master_write signals but do not see any transition/correct values in the address line ( i.e master_address).

-I tried for both burst mode and stride mode configurations separately, but do not see correct address where I want to write, which I provide in command_sink  "write address" field.

Can anybody suggest  where I am going wrong or how to solve this issue ?

Thanks,

Ashish.

[RichardTanSY_Altera]

Which Quartus version and devices are you using?

Please provide a screenshot on the issue that you are facing.

Please kindly provide the design, testbench & steps to simulate/duplicate the issue so I could further investigate.

Regards,

Richard Tan

[ShengN_Intel]

Hi Ashish,

Could you provide your waveform .wlf for taking a look?

Thanks,

Regards,

Sheng

[ShengN_Intel]

Hi,

I had tapped the write master waveform as attached pic.

Thanks,

Regards,

Sheng

[sstrell]

waitrequest is being held high by the system (assuming you're using Platform Designer here) for most of the time in the Signal Tap waveform you provided.  As long as waitrequest is held, the current command signals are held.  Something in the system is preventing the write.  It might help you show your PD system design.