Undefined output

[Altera_Forum]

Hi 

I have asked to write compare machine which compare 2 numbers with 4 bits. I made it by ussing XOR. My outputs dont react to the change in the inputs, they undefined. The inputs works well with my test bench. You can see my code at attached files.

[Altera_Forum]

Dont post images, post the actual code. 

 The problem probably occurs because you have a local variable i, and a while loop. The variable is probably gets to -1 on the first iteration and then the code is never executed again.  But the main problem with the code is that while loops are not synthesisable. You will need to change the code to remove the loops.

[Altera_Forum]

I have 2 question 

1. I made initialize to i=3 don't i?(line 17) 2. what you mean in "while loops are not synthsisable"? and which other way can i implement the component? thanks

[Altera_Forum]

VHDL code is not a sequential program which a cpu is supposed to execute, so a while loop makes no sense.  

VHDL is rather a description language: you are supposed to 'describe' logic gate connections. Any VHDL code which is not convertible (we call this 'synthesizable') in terms of logic gates, signals and flip-flops will not work and can not work. As you pointed out, a while loop is good only for a test bench and simulation, where you actually need to generate artificially some sequential input states. VHDL Usually a comparator is conveniently described in VHDL with high level operators > and <. If you want to follow your 'bare metal' approach, you can use the 'generate' statement, like in the following example: http://fpgacenter.com/digit_dsgn/log_gates/comparator.php