we're trying to verify a circuit using Functional Simulation. We know that output signal goes to state '0' at the clock's rising edge. But we see the output switching delay.
So, the question is why Quartus takes into account transport delay in this simulation mode? Perhaps, we can turn off transport delays for functional simulation? Could anyone help us? Thank you!
It's unlikely that you're seeing a transport delay when performing a functional simulation. Are you saying the output is going low between the current and next clock edges?
As mentioned, try using the timing analyzer on the output path to see if the design is failing timing.