Urgent help in verilog code for cyclone 4 e

[Altera_Forum]

Hello, I am currently working on ALTERA DE2-115 kit cyclone 4 e. I want to display the count (0-9) with specific delay between every count. please provide code.

[Altera_Forum]

you'd get the code quicker if you wrote it yourself.

[Altera_Forum]

sir I am the beginner and I dont have much of knowledge of the verilog programming. I tried to write the code but the results are not as desired. please help.

[Altera_Forum]

We were all beginners once. Why not find a verilog tutorial and start learning, like everyone else did?

[Altera_Forum]

You won't learn anything by asking others to do your homework for you.

[Altera_Forum]

This is the code which I have written to check whether lcd displayes anything. tell me if I have made a mistake anywhere. 

 Diplaying Characters To The LCD via FPGA  ------------« Begin Code »------------ .. ... -------------------Write 'P'-------------------   when S9 =>  current_state <= S10;   LCD_DATA <= x"50";  LCD_ENABLE <= '1';  LCD_RW <= '0';  LCD_RS <= '1';   when S10 =>  current_state <= S11;  LCD_DATA <= x"50";  LCD_ENABLE <= '0';  LCD_RW <= '0';  LCD_RS <= '1';  -------------------WRITE 'Y'-------------------   when S11 =>  current_state <= S12;   LCD_DATA <= X"59";  LCD_ENABLE <= '1';  LCD_RW <= '0';  LCD_RS <= '1';   when S12 =>  current_state <= S13;   LCD_DATA <= X"59";  LCD_ENABLE <= '0';  LCD_RW <= '0';  LCD_RS <= '1';  -------------------WRITE 'R'-------------------   when S13 =>  current_state <= S14;   LCD_DATA <= X"52";  LCD_ENABLE <= '1';  LCD_RW <= '0';  LCD_RS <= '1';   when S14 =>  current_state <= S15;  LCD_DATA <= X"52";  LCD_ENABLE <= '0';  LCD_RW <= '0';  LCD_RS <= '1'; ... .. ------------« End Code »------------

[Altera_Forum]

This is the code written to display some numbers on lcd.  

  ASCII to Numbers/Letters  ------------« Begin Code »------------ .. ... -------------------Function Set-------------------  when S0 =>  current_state <= S1;   LCD_DATA <= "00110000";   LCD_ENABLE <= '0';  LCD_RW <= '0';  LCD_RS <= '0';  when S1 =>  current_state <= S2;  LCD_DATA <= "00110000";   LCD_ENABLE <= '1';  LCD_RW <= '0';  LCD_RS <= '0';   when S2 =>  current_state <= S3;  LCD_DATA <= "00110000";   LCD_ENABLE <= '0';  LCD_RW <= '0';  LCD_RS <= '0'; -------------------Reset Display-------------------   when S3 =>  current_state <= S4;  LCD_DATA <= "00000001";   LCD_ENABLE <= '0';  LCD_RW <= '0';  LCD_RS <= '0';   when S4 =>  current_state <= S5;  LCD_DATA <= "00000001";   LCD_ENABLE <= '1';  LCD_RW <= '0';  LCD_RS <= '0';   when S5 =>  current_state <= S6;  LCD_DATA <= "00000001";   LCD_ENABLE <= '0';  LCD_RW <= '0';  LCD_RS <= '0';  -------------------Display On-------------------  when S6 =>  current_state <= S7;   LCD_DATA <= "00001110";  LCD_ENABLE <= '0';  LCD_RW <= '0';  LCD_RS <= '0';  when S7 =>  current_state <= S8;  LCD_DATA <= "00001110";  LCD_ENABLE <= '1';  LCD_RW <= '0';  LCD_RS <= '0';  when S8 =>  current_state <= S9;   LCD_DATA <= "00001110";  LCD_ENABLE <= '0';  LCD_RW <= '0';  LCD_RS <= '1'; ... .. ------------« End Code »------------

[Altera_Forum]

Are you sure you wrote it? it's VHDL, not verilog. 

 Why not try compiling the code and putting it on the board, or even better write a testbench and try the code in a simulator?

[Altera_Forum]

I tried it just to check whether the logic of the program is correct. I also put it on the board, but the output is not as desired. The lcd screen was not getting clear either.

[Altera_Forum]

The actual task is transmission of stream of data via Ethernet. But I am not able to crack that either. I am stuck in this lcd code.

[Altera_Forum]

I highly suggest you write a testbench so you can debug your code to ensure the output is what you desire (you'll need that for ethernet anyway)