Hi,
I try to integrate a design in QSYS using component editor. First I started with Bottom-Up Component Design methodology described in Quartus II Handbook Version 11.0 Volume 1: Design and Synthesis. I put some HDL files in the appropriate list (hdls.jpg) but HDL analysis failed:
Error: Error (10867): Verilog HDL or VHDL XML Interface error at av_local_reg_rtl.vhd(58): port "local_data_in" has an unsupported type File: l:/projekte/hdl_designs/common/hdl/av_local_reg_rtl.vhd Line: 58
HDL code at line 58:
local_data_in : IN avlocal_data_type (NR_OF_AVLOCAL_REGS/2-1 DOWNTO 0);
Does QSYS do ot support types at ports? (Synthesis with Quartus is no problem)
The package with the definitions I provided to QSYS (hdls.jpg)
Jens
